Enabling & Support

Board designs

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

The interfaces of a board design should follow the same requirements as previously suggested for models intended for board-level simulation. All timing parameters, such as clock-to-output and propagation delays, which are affected by the interconnection between the board design and other equipment, should have a corresponding timing generic with a default value declared as a deferred constant in a separate timing package.

Two approaches are presented: the architecture containing the timing information of the board, and the architecture only containing the connectivity and a separate configuration declaration containing the timing.

The following design units are located in the library BoardDesign_Lib (vhd):


In this package, all timing parameters for the Board Design are defined as deferred constants; their value can be modified by re-analysing only the package body. (vhd)


This is an example of a simple board with three serially connected Bit Modulators. (vhd)


This architecture contains information on connectivity and timing related information. Selection of entity/architecture for the BitModulator is made here. (vhd)


This architecture only contains information on connectivity, no timing related information or selection of entity/architecture is made here. That is deferred to a configuration declaration. (vhd)


BoardDesign_ Configuration

Configures the board with the explicit timing of the design. If other timing is needed, a new configuration could be derived. The generics SimCondition and TimingChecksOn are propagated down the hierarchy. (vhd)

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