Documents Related to SOC and IP-Core-Based Design

Using VHDL in System-On-a-Chip Developments

High integration levels of microelectronics will be required to fulfil increasing performance demands. Implementations will move from traditional components towards more advanced single-chip systems. The design methodology will be to integrate complex building blocks.

• Author: Sandi Habinc (ESA/ESTEC TOS-ESM) (pdf)

Designing Space Applications Using Synthesisable Cores

Abstract at MAPLD 1999 (pdf)

Presentation at MAPLD 1999

This paper concentrates on how building blocks for microelectronics are developed in VHDL and how they are purchased, distributed and used in the scope of European Space Agency (ESA) activities, ranging from in-house developments to contractor work and from simple Field Programmable Gate Arrays (FPGAs) to complex System-On-a-Chip (SOC) designs.

• Author: Sandi Habinc (ESA/ESTEC TOS-ESM) (pdf)

Accelerated Verification of Digital Devices Using VHDL

This paper presents two aspects for improving the verification of microprocessors; program-less verification, and methods for handling large differences in abstraction level between a reference model and the actual design. Program-less verification is a type of pseudo random verification where the notion of a software program executing on the microprocessor has been abandoned.

• Author: Sandi Habinc and Peter Sinander (ESA/ESTEC TOS-ESM) (pdf)