ESA title
Enabling & Support

SEFUW: SpacE FPGA Users Workshop, 1st Edition

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics
Organized by: ESA, CNES, ATMEL
Date: 6, 7 November 2012
Contact persons: ESA:
Fee: No fee is charged


In the past, two series of events enabled the exchange of highly valuable information and experience among FPGA users, CAD vendors and FPGA vendors: the very successful past four editions of the “ATMEL Users Group workshops” ( and the 2009 “workshop on Fault Injection & Fault Tolerance in space FPGAs” ( Following that spirit, the initiative expands now toall FPGAs used in space: reprogrammable (SRAM and FLASH based) and one-time programmable (anti-fuse based).


All FPGAs share several design methodologies, yet each of them face specific challenges. The anti-fuse FPGAs are currently heavily used in most electronic equipment for space yet there are other emerging technologies too: Flash-based and SRAM-based.


The aim of this workshop is to address experiences in several topics related to FPGAs for space covering (not limited too):

  • general design, verification and test issues and good practices
  • performance achievements and potential problems
  • power consumptions achievements and potential issues
  • design tools performance, good practices and potential limitations
  • radiation mitigation techniques, tools and potential limitations(avoiding repetitions of what has already been presented at RADECS, NSREC and SEE Symposium)
  • companion non-volatile memory (when required) experience
  • package and assembly challenges
  • trends of FPGA usage in space applications
  • lessons learned: ensuring successful and safe use of FPGA in space applications
  • choosing the best FPGA type for our space application


Presentations from at least the major design groups (Primes) are expected, as well as updates from the major FPGA vendors for space: ATMEL, MICROSEMI and XILINX.


A discussion panel will be organized. Topic: Re-configurability for space.


The workshop duration will be 2 days.




Tuesday 6th November

Welcome by David Merodio Codinachs (ESA) and David Dangla (CNES)

Session 1European FPGA industry

·         FPGAs for space applications
Giorgio Macor, Atmel

·         “Mentor’s FPGA Implementation Flow for Atmel”, (soon to be available)
Olivier Takeznount, Mentor

·         Design flow Precision – IDS
Didier Campos, Atmel

·         IDS improvements
Didier Campos, Atmel

·         High Performance Partitioning
Hayder Mrabet, Flexras

·         ”NanoXplore”, (soon to be available)
Olivier Lepape, NanoXplore


Session 2 Space industry experiences

·         CNES: European FPGA products
David Dangla, CNES

·         Atmel FPGAs
Alfonso Gonzalo, EADS Astrium Crisa

·         The ATF280 in the Simbio-Sys instrument of BepiColombo
Vincent Carlier, IAS- Orsay

·         SVOM mission: ATF280F/AT697F data processing for real-time GRB detection and localization & ATF280E SpaceWire CEA IP recent developments
Hervé Le Provost, CEA

·         “ATF280 projects in Thales Alenia Space France”,
Xavier Chebanier, Thales Alenia Space

·         “IP implementations in FPGAs”, Presentation 1, Presentation 2 (soon to be available)
Mercier Maya, Maya Technologies


Session 3 Tools

·         Extending Atmel IDS flow
Nikos Andrikos, ESA/Torino

·         FT-UNSHADES 2. Adaptation of the platform for SRAM-FPGA reliability assessment
Miguel A. Aguirre, Universidad de Sevilla

·         A CAD flow for the Analysis of SEU Sensitivity of SRAM-FPGA Systems
Luca Cassano, University of Pisa



Wednesday 7th November

Welcome by David Merodio Codinachs (ESA) and David Dangla (CNES)

Session 1 Non-European FPGA industry

·         FPGAs for Space Applications
Ken O’Neil, Microsemi

·         “Xilinx FPGA space products” (soon to be available)
Joe Fabula, Xilinx

·         Panel: “Re-configurability for space”
Tim Pike (EADS Astrium)
Xavier Chebanier, (Thales Alenia Space)
Agustin Fernandez Leon, (ESA, TEC-EDM). Presentation.


Session 2 Space industry experiences

·         “Xilinx at EADS Astrium” (soon to be available)
Adam Taylor, EADS Astrium

·         Dynamically Reconfigurable Processing Module (DRPM), application on instruments and qualification of FPGA package
Björn Fiethe, IDA-TU Braunschweig

·         DRPM architecture overview
Jens Hagemeyer, University of Bielefeld

·         “Microsemi at EADS Astrium”, (soon to be available)
Ottmar Ried, EADS Astrium


Session 3 Tools

·         "Soft Errors in Partially and dynamically reconfigurable SRAM-based FPGAs"
Massimo Violante, Politecnico di Torino

·         Single Event Transient Effects on Microsemi ProASIC Flash-based FPGAs: analysis and possible solutions"
Luca Sterpone, Politecnico di Torino




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