ESA title
Enabling & Support

SOC Development Activities

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

A number of SOC development activities has been or is being performed under ESA contracts, led or supported by the Microelectronics Section:


A System-on-a-Chip for Small Satellite Data Processing and Control. SOC requirements for small satellites were specified, and a ChipSat design built around the LEON processor core was implemented and tested on FPGA. A software implementation of a CCSDS Telecommand/Telemetry (TM/TC) loop was developed and tested with this platform. (pdf)

  • Prime contractor: Surrey Space Centre, Guildford, UK
  • Date: Closed Q1/2003


The Spacecraft Controller On a Chip (SCOC) architecture, using the LEON processor, provides hardware TM/TC functionality, dual on-chip bus architecture to ensure high data throughput and various interface modules. The objective of this contract, called "Building Blocks for System On-a Chip", was to conduct an architectural feasibility study, to specifiy and to implement a first SCOC architecture based on the LEON1 processor core. This architecture was prototyped in an FPGA on the BLADE (Board for Leon and Avionics DEmonstration). Another objective was to gain experience with the integration of IP-cores of various origins into a single design. (pdf)

  • Prime contractor: Astrium SAS, Velizy (F)
  • Date: Closed Q2/2004


Followup to the SCOC1 contract, with the objective to finalise the architectural design for a SCOC-ASIC and to conduct a feasibility study on target ASIC technology. This implies updating the architecture (using LEON3 and new versions of other IPs), development of additional building blocks, verification by simulation and FPGA prototyping and synthesis to target technology. (pdf)

  • Prime contractor: Astrium SAS, Velizy (F)
  • Date: Started Q3/2006


AGGA3 is the next generation GNSS baseband ASIC, successor of the AGGA2, targeting in particular earth observation applications. Besides a GNSS block with front-end and multi-channel correlators, it integrates the LEON2 processor and several Spacewire interfaces. It is also an example for a SOC reusing IP's from diverse origin. (pdf)

  • Prime contractor: Astrium GmbH, Ottobrunn (D)
  • Date:Started Q1/2003


The COLE ASIC will merge the Leon2 SPARC processor with all bus interface support needed to implement spacecraft processing and control and to control mass memories or payloads. (pdf)

  • Prime contractor: Saab Ericsson Space, Gothenburg (S)
  • Date: Manufacturing Q3/2007


The SpaceWire Remote Terminal Controller ASIC is to be used for controlling scientific instruments and to process their data. The Leon2-FT SPARC processor constitutes the core of this circuit, to serve as a link between a satellite high-speed SpaceWire backbone network and local, low-speed CAN buses serving individual instruments. (pdf)

  • Prime contractor: Saab Ericsson Space, Gothenburg (S)
  • Date: Started Q1/2005

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