Enabling & Support

Verification of board designs

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

A test bench should be developed for the board design analogous to the test bench for a model intended for board-level simulation. A test generator with one or multiple architectures with test suites should be instantiated together with the board design in the test bench architecture. Selection of simulation conditions and test suites should be done by using configuration declarations with the same names as have been defined for the verification of models intended for board-level simulation: WorstCaseTest, TypCaseTest and BestCaseTest.

The following design units are located in the library BoardDesign_TB_Lib (vhd):

 

TestGenerator (vhd)

 

TestGenerator - Timing

This test suite will test all timing constraint checkers (both with and without timing violations). The test suite can be executed for different simulation conditions using the SimCondition generic in the entity. (vhd)

TestBench (Structural)

The test bench connects the test object and the test generator. (vhd)

WorstCaseTest

Configuration declaration selecting the timing test under Worst Case simulation conditions. (vhd)

TypCaseTest

Configuration declaration selecting the timing test under Typical Case simulation conditions. (vhd)

BestCaseTest

Configuration declaration selecting the timing test under Best Case simulation conditions. (vhd)

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