ESA title
Enabling & Support

Verification of models for board-level simulation

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

Model verification is performed to ensure that the model fulfils its requirements, both on functionality and timing.

The following design units are located in the library BitMod_TB_Lib (vhd):



This package defines the MISR subprogram used by the Test Generator for the verification of the Bit Modulator. (vhd)


Since several functions are normally used in more than one architecture of the test generator, sub-programs could be declared in a separate package or in the declarative part of the entity. (vhd)


The test generator should generate stimuli and acquire response data for comparison with the expected results in order to verify the behaviour of the test object. The test generator could have more than one architecture, implementing different test suites verifying different functions. An architecture of a test generator should include processes that generate the test suite, evaluate test results, generate list files, perform output data compression etc.

For complete verification, all external objects should be modelled in the test generator, e.g. protocol machines, bus interfaces etc. allowing for generation of non-nominal stimuli such as inducing incorrect or corrupted accesses, error injection etc., which is normally only possible when having full controllability and observability.

TestGenerator (Functional)

This test suite will test the full functionality of the model, except the mode when Built In Self Test, BIST, is activated. The activation of the BIST would preclude the test suite to be evaluated using fault simulation. The BIST is tested in the architecture X_Handling. (vhd)

TestGenerator (X_Handling)

This test suite will test the following: all inputs will be applied all nine Std_Logic values; all checkers for unknown values on inputs; the handling of each unknown input value will be checked; the propagation of each unknown input value will be checked. (vhd)

TestGenerator (Timing)

This test suite will test all timing constraint checkers (both with and without timing violations). The test suite can be executed for different simulation conditions using the SimCondition generic declared in the entity. (vhd)

TestBench (Structural)

The test bench contains the model to be verified and a test generator. (vhd)


Configuration declaration selecting the functional test suite and deactivates the timing checkers of the Bit Modulator. (vhd)


Configuration declaration selecting the test suite for verification of the checker for unknown inputs and the BIST mode. (vhd)


Configuration declaration selecting the timing test under Worst Case simulation conditions. (vhd)


Configuration declaration selecting the timing test under Typical Case simulation conditions. (vhd)


Configuration declaration selecting the timing test under Best Case simulation conditions. (vhd)

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