Electronic System-Level (ESL) Day - September 2011
The continuous increase of transistor density on a single die is leading towards the production of more and more complex systems on a single chip, with an increasing number of components starting to be integrated into a single System-on-Chip (SoC): a single device containing multiple functions, e.g. processor, memory, communication primitives, etc. To support the design of those complex systems, new families of tools are needed. They are generally grouped in the branch known as Electronic System Level (ESL) and they provide support for tasks like design space exploration, system level verification, and performance analysis. The ESA Electronic System-Level design presentation day focuses on the activities that are being undertaken at the European Space Agency in order to start introducing some of those tools in the design and development cycles of digital electronics for space. In particular, the presentations will focus on techniques to efficiently create and use models at a higher than RTL abstraction, and especially on how to employ them to enable concurrent design of the hardware and software design portions. It will be demonstrated how, often, this brings added value with respect to classical RTL design approach.
Electronic System Level design at ESA: a hardware perspective
Luca Fossati (ESA/ESTEC) - PDF
A short introduction, of what the Electronic System Level design methodology is, will be given, presenting its strengths, weaknesses, and the problems it tries to solve. Main focus of the talk will be a broad overview of the activities undertaken by TEC-EDM in this field.
Hardware Modeling using Virtual Platforms
Thomas Schuster (IDA) - PDF
A Virtual Platform is a software program mimicking the behavior of a hardware system; as such it is more flexible than a hardware prototype, and it is easier to extract performance metrics and to analyze/debug the execution. In addition to developing the Virtual Platform Infrastructure itself (called SocROCKET), the activity being presented focuses on creating the high-level models of some of the most used IP-Cores from Aeroflex Gaisler's GRLIB, namely the AMBA interconnection, the MMU/cache block, the memory, interrupt controllers, and the timer. All models are implemented in SystemC and provide TLM2.0 communication interfaces for different levels of abstraction. ISS and peripherals have been jointly integrated in a novel SystemC modeling library. The library provides transactors for co-simulation of RTL components, an advanced meta-build system (WAF), a template based platform generator and other features to raise productivity. To highlight the capabilities of models and library, we will present a demo-design along our experiences and results of a design space exploration.
Design of the SystemC model of the LEON2/3 processor
Luca Fossati (ESA/ESTEC) - PDF
During the last decade the LEON Sparc V8 CPU has become a de-facto standard for diverse aerospace applications. Fast compiled simulators are available to facilitate software development and verification. Because of the ever-growing complexity of modern space applications this system should be complemented by a flexible Virtual Platform (VP). The talk presents the SystemC model of the LEON2 and LEON3 processors and the TRAP tool used to build such models.
Design of the SystemC model of the SpaceWire-b CODEC
Nikos Mouratidis (Qualtek) - PDF
The advent of SystemC brought order and introduced solid methodology foundations to the C/C++ system modelling efforts of the past. The introduction of TLM provided the tools for the construction of focused and efficient models. The presentation describes the development of a SystemC IP Core implementing the SpaceWire-b communication protocol as contained in the standard ECSS-E-ST-50-12C. Creating the SpW models for ESA presented a set of challenges in applying the TLM methodology and utilizing the associated infrastructure: the combination of abstraction levels in a single model; the comparison to the timing and speed of an existing RTL core; implementation of transactors and development of transactor-based testbenches to take advantage and draw conclusions on the aforementioned comparison; dealing with the peculiarities of vendor-specific tools in order to obtain a vendor-independent model; assessment of trade-offs between model accuracy and execution speed; the assessment of implementation alternatives and the identification of the more efficient ones. The presentation traces the aforementioned issues, and discusses, beyond the characteristics and objectives of the model itself, the challenges, the approach, and the experience gained throughout the development of the SpW TLM model.
SoCKET: SoC toolKit for critical Embedded systems
Vincent Leftz (Astrium) - PDF
The evolution of technology (SoC integration) and application needs lead to design more and more complex embedded systems, both at hardware and software levels. Mastering this complexity, in order to improve the time cycle, the costs of the design, and the validation/qualification of the critical embedded systems, is a key point to ensure the success of our future industrial projects. Astrium has contributed (and coordinated) the SoCKET (http://socket.imag.fr/index-en.htm) collaborative project combining the efforts of industrial and academic partners, in order to propose a ”seamless” development flow, integrating the equipment qualification, from the system level to the Integrated Circuits (ICs) and the associated embedded software, compliant with the applicable norms (such as DO/ARP for aeronautic and ECSS for space). This ”seamless” design flow is built upon technical pillars: 1) High Level Synthesis, 2) Heterogeneous simulation techniques, 3) IPs encapsulation and interoperability (IP-XACT) and 4) Assertion Based Validation Techniques. This talk will present the result of this project, and the proposed design flow with a focus on Astrium return of experience regarding HLS and ABV techniques, and also SystemC/TLM modelling techniques. We will conclude on the highlighted needs regarding an ESL ecosystem for space application domain.
Overview of the ASSERT and the TASTE toolchains
Maxime Perrotin (ESA/ESTEC) - PDF
ASSERT aims at developing a reliable and scientific approach for systems and software engineering; started on this basis, the TASTE project will broaden the scope of the toolset’s targeted systems, by including hardware component functionality. An overview of the activities will be given in the presentation.
The TASTE project: results and lessons learnt
Marc Pollina (M3 Systems) - PDF
The TASTE project (2010-2011) aimed to expose the TASTE technology to industrial experts and real cases, with the intention to assess its level of maturity, while opening the way for new HW/SW codesign concepts to be integrated in the toolset. To reach these objectives, a simple hardware support has been integrated to TASTE, and the technology has been exposed to a representative case study: the design of a satellite demonstrator, shared between an embedded GPS payload and a TM/TC encryption service platform. This talk will present the results of the TASTE project, as well as the lessons learnt about the TASTE technology.
Extending TASTE through integration with SpaceStudio
Guy Bois (SpaceCodesign) - PDF
SpaceStudio is a fully integrated Electronic System Level (ESL) development environment for the creation, simulation and monitoring of complex HW/SW codesigned systems-on-chip. The methodology followed by SpaceStudio is a combination of a refinement-based method going through several levels of transactional level models (TLM) and an explicit mapping-based method of platform-based design. As an extension to the TASTE project, the integration of SpaceStudio with TASTE has been studied. The objectives were to explore the possibility of such integration, and to show that TASTE would greatly benefit from SpaceStudio extended capabilities for HW/SW codesign of a complex system-on-chip. This presentation will give an overview of the results of this study.
Hardware Design using High-Level synthesis
Laurent Hili (ESA/ESTEC) - PDF
High-Level Synthesis (HLS) is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. The presentation will give an overview of the HLS methodologies, stressing how they are fundamental in the creation of Deep Sub-Micron high-gate count designs.
Conclusion, Q&A, and Future Perspectives
Luca Fossati (ESA/ESTEC) - PDF
Last update: 27 September 2011