LEON2-FT - HDL

The LEON2-FT processor is the SEU (Single Event Upset) tolerant version of the LEON2 processor. Flip-flops are protected by Triple Modular Redundancy and all internal and external memories are protected by EDAC or parity bits.

Overview

The LEON VHDL model implements a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture. It is designed for embedded applications with the following features on-chip: separate instruction and data caches, hardware multiplier and divider, interrupt controller, debug support unit with trace buffer, two 24-bit timers, two UARTs, power-down function, watchdog, 16-bit I/O port and a flexible memory controller. New modules can easily be added using the on-chip AMBA AHB/APB buses. The VHDL model is fully synthesisable with most synthesis tools and can be implemented on both FPGAs and ASICs. Simulation can be done with all VHDL-87 compliant simulators.

The original LEON design includes advanced fault-tolerance features to withstand arbitrary single-event upset (SEU) errors without loss of data. The fault-tolerance is provided at design (VHDL) level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools.

Area/Speed Results

(Configuration as in Atmel AT697E ASIC, including PCI, but FT reduced to external memory EDAC):

xc2v3000 : 24% registers, 37% blockram, 79% LUT
ax2000 : 85% sequential, 124% combinatorial, 112% total

Developer

Jiri Gaisler, ESA/ESTEC, 1999

Current Release

version 2014.1, released 15 July 2014

Special licensing restrictions

ESA can grant licenses for the use of the IP core only for activities performed in the frame of an ESA Programme.
The model contains stubs for FPU's, MMU and a PCI interface, but neither the FPU, the MMU nor the PCI cores are actually supplied with the model.

Last update: 15 July 2014

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