SystemC IP-Cores
Various activities have been or are being undertaken to create high level models of the VHDL IP-Cores most used in the Systems-on-Chip (SoCs) employed at the European Space Agency.
Examples of such IP-Core include the LEON2 and LEON3 processor cores, restricting the modeling to the integer unit; the other elements which are indeed part of the LEON2/3 SoCs are being developed as separate SystemC IP-Cores. Some of them are the L1 cache, Sparc V8 Reference MMU, Interconnection compliant with the AMBA© AHB™ and APB™ protocols, Memory Controller, etc. For more details see the individual pages about the IP-Core models and the SoCROCKET Virtual Platform.
Additional IP-Cores which are currently part of the NGMP Architecture are also being considered.
Examples of such IP-Core include the LEON2 and LEON3 processor cores, restricting the modeling to the integer unit; the other elements which are indeed part of the LEON2/3 SoCs are being developed as separate SystemC IP-Cores. Some of them are the L1 cache, Sparc V8 Reference MMU, Interconnection compliant with the AMBA© AHB™ and APB™ protocols, Memory Controller, etc. For more details see the individual pages about the IP-Core models and the SoCROCKET Virtual Platform.
Additional IP-Cores which are currently part of the NGMP Architecture are also being considered.
The following Figure shows the current development status: green blocks indicates IP-Cores under development, blue completed and available, and black not yet under development.
The SystemC IP-Cores are written using the C++ language and they are based on the SystemC library for modeling the IP structure and the flow of time and on the new TLM 2.0 standard for modeling the communication interfaces.
Please refer to the Licensing page (accessible from web-site right menu) or the individual pages of the SystemC IP-Cores for more details on the steps necessary to obtain the SystemC IP-Cores source code and the relative license.
