ERC32 VMEbus Interface (EVI32) - specification, synthesizable VHDL model and ASSP component
The EVI32 synthesizable VHDL core is a 32-bit VME interface circuit designated to interface the ERC32 processor chip set to the VMEbus.
The EVI32 fully adheres to the IEEE 1014-1987 VMEbus standard, and is compatible with the commercial VMEbus specification.
The EVI32 IP Core can act as a system controller and provides both master and slave interfaces. It comprises the following functions:
- A32/A24/D32/D16/D8 master and slave interface;
- Interrupt handler;
- Single level arbiter (SGL);
- VME bus timer;
- Optimised D16 interface;
- Four mailboxes for multi-processor communication;
- Minimised usage of external buffers;
The EVI32 specification and VHDL design is a result of an internal ESTEC development.
The design has been implemented in an FPGA and is suitable for implementation in radiation hard or tolerant ASIC technologies.
The functional specification is available for download in Adobe PDF format (see menu on the right).
The synthesizable VHDL model with testbenches are available under the standard ESA licensing conditions.
The VHDL core, adapted to the ERC32 three chip and single chip processors, as well as the 21020 DSP, has been implemented by Astrium Velizy to the T7907E chip under ESA contract 13345. This chip shall be commercialised by Atmel.
Area and speed
Total LUTs: 1363 of 2910 (46%)
Logic resources: 1446 ATOMs of 2910 (49%)
Running at 20 MHz
Jiri Gaisler, ESTEC/ESA, 1997
version 1.3, 04-Dec-1998
This release contains the complete ERC32 VHDL models, the EVI32 version 1.3 models and a test bench.
Special licensing restrictions
Last update: 15 September 2017