The aim of the Time Distribution Protocol (TDP) is to synchronize time across a SpaceWire network.
The SPWTDP VHDL IP-Core does this by an initiator writing a CCSDS Time Code using an RMAP command placed in a SpaceWire packet, transferring it across the SpaceWire network and then extracting the CCSDS Time Code at the target, and by means of SpaceWire Time-Codes the time instant at which CCSDS Time Code becomes valid (synchronization event).
The implementation of the jitter and drift mitigation is based on a simple time interval measurement of the incoming SpaceWire Time-Codes using the local clock, gathering statistical information which is then used to calculate an average correction value that is applied to a locally generated signal which is free from jitter and local drift. The variance of the corrected locally generated signal is limited to one period of the local clock.
Area and Speed Results
The core is generic RTL code which can be synthesized for a range of ASIC and FPGA technologies including Actel and Xilinx FPGAs.
Examples of resource usage on some Xilinx technologies is given below; note that no significant effort was spent in trying to optimize those results.
Virtex 5Q – XQ5VFX130T:
Number of Used Slice Registers: 728 (1%)
Number of Used Slice LUTs: 2339 (2%)
Number of occuppied slices: 940 (4%)
Max clk frequency: 97MHz
Aeroflex Gaisler - 2014
ESA can grant licenses for the use of the (R)CCIPC IP core only for activities funded by the Agency (ESA projects).