AHBR - HDL
The AHBR IP-Core implements an AMBA AHB to AMBA AHB bus bridge, where the two busses are clock synchronous clocks with defined frequency ratio function.
AHBR is an IP-Core implementing the functionality of an AMBA AHB to AMBA AHB bus bridge. As shown in the Figure below, AHBR is composed of the following functions:
For more details please refer to the documents accessible on the top right of this webpage.
Area and Speed Results
The core is generic RTL code which can be synthesized for a range of ASIC and FPGA technologies including Actel and Xilinx FPGAs.
Examples of resource usage on some Xilinx technologies is given below; note that no significant effort was spent in trying to optimize those results.
Virtex 4QV – XQR4VLX200:
Virtex 5Q – XQ5VFX130T:
Astrium - O. Corvoisier, Marc Soury - 2008
No special licensing conditions apply. For more information refer to the ESA IP-Cores licensing page.
Last update: 6 January 2014