AHBR - HDL


The AHBR IP-Core implements an AMBA AHB to AMBA AHB bus bridge, where the two busses are clock synchronous clocks with defined frequency ratio function.
 
Overview
 
AHBR is an IP-Core implementing the functionality of an AMBA AHB to AMBA AHB bus bridge. As shown in the Figure below, AHBR is composed of the following functions:
  • AHB Slave interface
  • AHB Master interface
  • Interconnection block between AHB Slave interface and AHB Master interface
The core supports single and burst AHB transfers and only ERROR and OKAY responses. It also includes write protection functionality on a programmable range of addresses.
For more details please refer to the documents accessible on the top right of this webpage.
 
 
AHBR IP-Core Block Diagram
 
AHBR IP-Core Block Diagram
 
 
 
 
Area and Speed Results
 
The core is generic RTL code which can be synthesized for a range of ASIC and FPGA technologies including Actel and Xilinx FPGAs.
Examples of resource usage on some Xilinx technologies is given below; note that no significant effort was spent in trying to optimize those results.

Virtex 4QV – XQR4VLX200:
Number of Used Slices: 539 (0%)
Number of Used Slice FFs: 608 (0%)
Number of Used 4 inputs LUTs: 714 (0%)

Virtex 5Q – XQ5VFX130T:
Number of Used Slice Registers: 608 (0%)
Number of Used Slice LUTs: 531 (0%)


 
 
Developers
 
Astrium - O. Corvoisier, Marc Soury - 2008
 
 
Licensing Conditions
 
No special licensing conditions apply. For more information refer to the ESA IP-Cores licensing page.
 
 
 
Last update: 6 January 2014

 •  SCOC3 (pdf) (http://microelectronics.esa.int/mpd2007/SCOC3-MPD2007.pdf)
 •  AHBR Specs. (https://amstel.estec.esa.int/tecedm/ipcores/AHBR_specification_architecture.pdf)
 •  Licensing (http://www.esa.int/TEC/Microelectronics/SEM6SCV681F_0.html)