System-Level Modeling in SystemC


In the past, the hardware design world standardized on two languages: VHDL and Verilog. Lately, there has been a growing interest in complementary languages that could be employed for descriptions at a much higher level of abstraction. The driving forces behind such efforts are the simultaneous increase in design complexity, with multi-million gate designs, and the increase in pressure to get designs out faster with first-time design success. Among those high-level languages, SystemC, System-Verilog, and SpecC represent the most widespread. These languages fuse a well-known syntax with powerful constructs, enabling the modeling and simulation of complex systems; in particular SystemC has grown more and more popular.
 
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++, together with signals, events, and synchronization primitives, deliberately mimicking the hardware description languages VHDL and Verilog. While such languages are often used for Register Transfer Level descriptions, SystemC is generally applied to system-level modelling, architectural exploration, software development, functional verification, and high-level synthesis. SystemC is often associated with Electronic System Level (ESL) design, and with Transaction-Level Modelling (TLM).
 
 
 
Hardware Description Languages and Abstraction Levels
 
SystemC offers real productivity gains by letting engineers design both the hardware and the software components together as these components would exist on the final system, but at a higher level of abstraction. This means that it is possible to concentrate on the actual functionality of the system more than on its implementation details. Moreover, since the detailed implementation has not been finalized yet, it is still possible to perform consistent changes to the design, enabling an effective evaluation of different architecture alternatives (including the partitioning of the functionalities between hardware and software). SystemC is also characterized by a high execution speed; note that this high speed is not only due to the SystemC simulation engine itself, but it is also caused by the high abstraction level generally used for SystemC based system descriptions.
 
 
Transaction Level Modeling (TLM)
 
Using a language for System-Level modeling, such as SystemC, is not enough for building an effective simulatable model: it is also necessary to define modeling styles and interoperability rules among the various models. Moreover, it is difficult to determine which features to abstract (and to what extent), nor how to use the remaining features to create an executable model that allows meaningful, efficient, and accurate analysis of the intended system. Transaction Level Modeling (TLM), an idea first introduced by the University of California, Irvine, is now widely accepted as an efficient technique for abstract modeling of communication and, according to recent research, computation. Indeed, we define Transaction Level Modeling (TLM) as the modeling style where at least one, between communication and computation, introduces an approximate concept of time.
The underlying concept of TLM is centered on modeling only the level of detail that is needed; by eliminating the un-necessary details, design teams can obtain huge gains in simulation speed. At this level, changes to the design are also relatively easy and cost effective because the development team has not yet delved in low-level details such as, for example, parallel bus implementation versus a serial bus. Transaction-Level models are not only useful for embedded software development, but also for other activities that are related to performance evaluation.

In 2008, the OSCI committee has proposed a TLM library composed of a set of SystemC primitives that allow designers to implement several Transaction Level communication protocols with different degrees of accuracy.
 
 
 
Last update: 18 November 2010


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Related links

 •  OSCI SystemC and TLM (http://www.accellera.org/home/)