EDAC - HDL
The EDAC (Error Detection And Correction) IP Core is a set of encoders/decoders supporting data widths from 4 to 64 bits, providing Single Error Correction and Double Error Detection, and in some cases Double Error Correction and Single Bank-error Detection.
EDAC Encoders/Decoders are frequently used for protecting data in aerospace applications.
Actel 54SXA - 54SX08A
(Please note that the EDAC implementation is purely combinational).
EDAC_RTL Total Cells 367 of 768 (48%)
version 0.6, August 2005
An encrypted Modelsim (5.6e) model is available for evaluation purposes.
For a history of bug reports and fixes, modifications, upgrades, etc, please refer to the EDAC IP Core Release Notes.
Special licensing restrictions
Last update: 9 September 2011