Spacecraft operate in a hostile environment, where the electronics are exposed to ionising radiation. Over the long term, the received total dose causes accumulation of local electrical charges that can cause misbehaviour by or destruction of the hardware. Sporadically, heavy ions can enter the hardware, creating Single Event Upsets (SEUs) which are able, for example, to alter the state of bits in the memory.
The effects of radiation can be avoided if electronic components are built using a specific technology, known as ‘rad-hard’ (radiation hardened). In particular, the computer processors used for spacecraft are specific to that purpose, although they are based on standard architectures such as MIL-STD-1750, SPARC or digital signal processors.
The hostile space environment constraints the computer system hardware, which in turn imposes the requirement to use specific cross compilers for the production of on-board software. In addition, special features are added to these compilers. These features are not always specifically linked to the space domain, but are useful in complying with some of the space on-board software requirements (for example: the possibility to modify the software in flight while minimizing the amount of memory to upload, predictability properties of scheduling).
To support the radiation hardened processors, ESTEC needs to invest in the associated compilers. While the traditional method of procuring compilers from proprietary vendors continues, open source compiler technology is supported as well, in order to benefit from a double source and secure the future of the space processors.
For the choice and procurement of space microprocessors, ESA/IPC/95/121 recommends the MIL-STD-1750A (and 1750B) microprocessor for 16 bit applications [MA31750] and the SPARC architecture for 32 bit applications [ERC32 Sparc V7 and LEON Sparc V8].
For the programming languages of these processors, ESA/IPC/96/73 limits the supported languages to C [ANSI/ISO 9899] and Ada83 [ANSI/MIL 1815A]. Ada 95 [ISO/IEC 9638] and some real-time Java implementations are supported for the 32 bit applications.
Cross compilation systems
The compiler environments depend, at least for the back-end, on the target computer. An overview is available for the MA31750, the DSP21020, the ERC32, and the Leon (see right-hand navigation menu).
The ESA Ravenscar Benchmark (ERB) is a compiler test suite to evaluate efficiency (size and performance) of available compiler systems and kernels for ERC32 and LEON, and of different language constructs, kernel functions, and library implementations. ERB has the purpose of filling the gaps present in other test suites. It aims at providing a synthetic benchmark for comparing the efficiency of various Ada Ravenscar implementations running on the ERC32 and LEON systems. The ERB harness test suite evaluates an Ada run time in terms of: execution time, memory footprint (i.e., the memory size/overhead of the kernel, libraries and run time system to host an application) and stack size requirements, at the same time. Additionally, it can compare the different Ada runtime results with non-Ada systems, such as RTEMS.
Some activities are being performed by Edisoft in cooperation with Syderal, Aonix and Astrium Space Transportation to provide the consolidation of the development environment for LEON, identification of the development environment weaknesses, implementation of improvements and the propose of future developments.
Various studies have been performed to investigate the best use of coding languages for space software, with respect to criteria such as the criticality, the object orientation or the use of Java.
Last update: 23 July 2008