ESA title
Enabling & Support

SPI - Serial Peripheral Interconnect

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ESA / Enabling & Support / Space Engineering & Technology / Onboard Computer and Data Handling

Space equipments need a standard serial digital solution for the interconnection of standard peripherals/components within a unit.

The board and pin real estate savings comparing a serial digital solution to a parallel I/O bus are significant, and have earned Serial Peripheral Interconnect (SPI) a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher end 32-bit processors such as those using ARM, MIPS, or PowerPC and with other microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. ASIC or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as on-PCB one.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols.

SPI is used to talk to a variety of peripherals, such as Sensors: temperature, pressure, ADC, touchscreens, video game controllers Control devices: audio codecs, digital potentiometers, DAC Camera lenses: Canon EF lens mount Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11 Memory: FLASH and EEPROM Real-time clocks LCD displays, sometimes even for managing image data Any MMC or SD card (including SDIO variant) For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.

JTAG is essentially an application stack for a 3-wire SPI flavour, using different signal names: TCK not SCK, TDI not MOSI, TDO not MISO. It defines a state machine (driven by a TMS signal instead of a chip select line), protocol messages, a core command set, the ability to daisy-chain devices in a "scan chain", and how vendors define new commands. The devices in a scan chain are initially treated as a single device, and transitions on TMS update their state machines; once the individual devices are identified, commands may be issued that affect only one device in that scan chain. Different vendors use different JTAG connectors. Bit strings used in JTAG are often long and not multiples of 8 bit words; for example, a boundary scan reports signal state on each of several hundred pins.