ESA title
Enabling & Support

Internal Research and Stage Reports

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

This section presents a summary of the internal research done by various Young Graduate Trainees, Spanish Trainees, Stagiaires and Research Fellows in the Microelectronics Section.

My BRAVE Journey

A summary of two years spent working on several topics, mainly related to the new BRAVE FPGA: preparation of a BRAVE Development Kit Environment, development of a BRAVE Demonstrator Application (image/video processing application with using an HDMI video stream), implementation of an Open ESA FPGA Benchmark Suite (to measure and compare FPGA devices and their CAD tools from different vendors), radiation test of a Xilinx Kintex-7 FPGA. 

  • Date: Sep 2015 – Set 2017
  • Author: Thomas Lange (pdf)


Radiation Effects on SRAM FPGA designs, UKube Static SEE Rates

SEE rate prediction using various methodologies applied to an actual design. The design under study is the Janus payload from EADS Astrium developed for the UKube satellite.

  • Date: Sep 2011 – Feb 2013
  • Author: Sotirios Athanasiou (pdf-1) - (pdf-2)


Innovative Space Electronics Design Techniques
Novel work was undertaken in order to improve and optimize the way space electronics can be designed. Focused on the DARE/UMC 90 and 180 nm technologies, he contributed to the development of tools and characterization data to improve and optimize the design and development of microelectronic circuits for Space applications. Sotirios enhanced existing compact transistor models to include TID and SET effects. He also studied radiation effects in UMC 90 nm low leakage nMOSFETs using TCAD and Matlab models. He designed a wideband amplifier and a test vehicle for the characterization of SET in UMC 180, and for the calibration of the new simulation models.

  • Date: Sep 2011 – Feb 2013
  • Author: Sotirios Athanasiou (ppt)


HV rad tolerant CAN transceiver design
HV rad tolerant CAN transceiver design on DARE UMC 180nm

  • Date: May 2011 – Feb 2013
  • Author: Scott Lindner


P&R for Atmel FPGAs
Integration of Atmel IDS tool and VPLACE tool for Place and Route; benchmarking of the combined flow.

  • Date: Jan 2011 – Jan 2013
  • Author: Nikolaos Andrikos (ppt)


Trends in ASIC and FPGA utilisation in ESA missions

  • Date: Mar-Jun 2012
  • Author: Roger Boada (pdf)


Extraction of new IP Cores from SCOC3 Database

  • Date: Jan-Jun 2012
  • Author: Raphael Job


Reliability-aware Design methodologies for Embedded Systems on Multi-FPGA Platforms

  • Date: March 2010 - Feb 2011
  • Author: Chiara Sandionigi (pdf)


Test and debug of ATMEL 280K FPGA design kit

  • Date: July 2010 - Sept 2011
  • Author: Javier Galindo Guarch (ppt)


Fault-Tolerance in reprogrammable FPGAs
Fault-tolerance in systems based on reprogrammable FPGAs. Generic and parametric SEE radiation test vehicles for such FPGAs.

  • Date: August 2010 - 2011
  • Author: Stavros Tzilis


ESA IP-Cores Managment Website
Creation of a Database and active website for the management of the ESA IP-Cores (tracking requests, licenses, etc.)

  • Date: Feb-Jul 2011
  • Author: Rocío Moyano Vergara


FT-Unshades 2
Drafting of Requirements and Applications for the next generation of FT-UNSHADES systems.

  • Date: Oct - Dec 10
  • Author: Juanma Mogollón Garcia and Javier Nápoles


Analysis of radiation effects in programming logic of Atmel FPGAs
Development of tools and mitigation techniques similar to those developed for Xilinx FPGAs (e.g. Star/RoRA): SUSANA, JONATHAN. Optimization of placement algorithms for Atmel FPGAs.

  • Date: July 09- Dec 10
  • Author: Filomena Decuzzi (pdf)


Fault Tolerance techniques in SystemC
Study of reliability using the ReSP SystemC simulation platform.

  • Date: Sep 08-Dec 08
  • Author: Antono Miele (ppt)


Fault tolerance analysis by netlist static exploration

  • Date: Jun 07 - May 08
  • Author: Simon Schultz (pdf)


SoC Design Methodologies
Design and use of a SystemC-base simulation plaform (ReSP) for Multi-Core Systems-on-Chip design. Study of innovative techniques for Hardware/Software co-design.

  • Date: Sep 06-Sep 08 (Beltrame), Sep 07-May 08 (Fossati)
  • Author: Luca Fossati, Giovanni Beltrame (pdf)


Preparation of a SystemC model of LEON2 for ReSP

  • Date: Oct 07 - May 08
  • Author: Jose Fernandez Alcon (pdf)


Architecture-aware rad hard mitigation techniques for DSP designs

  • Date: Oct 07 - Jan 08
  • Author: Pilar Reyes Moreno (ppt)


OCP: Open Core Protocol
An ESA internal case study, converting the CAN IP core to OCP

  • Date: June 2006
  • Author: Marta Posada (ppt)


FT-UNSHADES benchmarking and testing
FT-UNSHADES benchmarking and testing using the LEON2-FT processor as a test-case.

  • Date: Jun 06 - Aug 07
  • Author: G. Lucia (ppt)


Atmel AT40K FPGA analysis
Atmel AT40K FPGA analysis; implementation of the SpaceWire-b CODEC on such FPGA.

  • Date: Mar - Aug 2008
  • Author: Hakan Helzenius


Magillem SOC Development
System On Chip Development Based on Magillem 2.3SE.

  • Date: December 2005
  • Author: Mattias Carlqvist (pdf)


SystemC Methodology
Research on New Design Methodology using SystemC.

  • Date: August 2005
  • Author: Nicolas Laine (pdf)


System on Chip design methods and IP Reuse
System on Chip design methods and IP (intellectual property) reuse. Small system on chip design (simulation model) built around an AMBA AHB bus used by Leon processor, and 2 Space wires.

  • Date: Mar - May 04
  • Author: Xavier Lbos


SEU Simulation Tool

  • Date: Jul 03 - May 04
  • Author: Daniel Gonzalez Gutierrez(pdf)


80S32 Board
Specification of a Validation Board for the 80S32 8-bit Microcontroller.

  • Date: May 2003
  • Author: Sami Heinisuo (pdf)


The objective of the activity was to develop a signal generator for GALILEO and GPS signals. At first, a software signal generator was implemented in Matlab. The software signal generator has to serve to rapidly prototype different transmitter configurations, algorithms and techniques, assess the performance of GALILEO signals, and create initial designs for further hardware implementations. Then, the signal generator was ported to VHDL code. A hardware implementation, e.g. on FPGA, will introduce higher efficiency due to its higher processing speed, allowing real-time generation of the signal.

  • Date: January 2003
  • Author: Juan Jose Borras Aguilar, YGT at ESTEC (pdf)


PCI Core - AMBA Bus interface and Additional Documentation for the IP-Core developed by R. Locatelli.

  • Date: Nov. 2000
  • Author: Elsa Lama Vaquero (pdf), (pdf)


Development of a Master/Target PCI VHDL Core.

  • Date: Sep. 1999
  • Author: Riccardo Locatelli (pdf)


ASIC Implementation of a Filter Bank Analyzer Based on CSD Code.

  • Date: Sept. 1999
  • Author: Christian Rosadini (pdf)


YGT Report in 2 parts: Digital Autocorrelation Spectrometers for Space-Borne Applications and Design of a Parallel FFT Processor Using Fixed Point Arithmetic and CSD Multiplication.

  • Date: August 1995
  • Author: Roland Weigand, YGT at ESTEC (pdf)

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