RTEMS-SMP Improvement for LEON multi-core

Contractor(s): Embedded Brains GmbH (Germany)

ESA Budget: 95 kEuro

YoC: 2017

Background and justification

With new space qualified multi-core processors becoming available, the need for parallel programming models to exploit the performance of these type of processors is paramount. In particular in the area of science data handling, the symmetric multi-programming (SMP) paradigm was gaining traction, but no support was available in real-time operating systems targeting LEON based processors. We ran two parallel studies to investigate the needs for a development environment for LEON multicore, that provided SMP support for the open source RTEMS operating system, and an implementation of the MTAPI parallel programming library (available at https://essr.esa.int/project/mtapi-for-leon-multicore), which was benchmarked on the GAIA VPU application with very promising results.

Objective(s)

The objective of the RTEMS-SMP Improvement for LEON multi-core activity was to improve the prototype SMP implementation from the earlier studies to production level quality, such it can be used in future space missions, in particular in the context of payload software, running on either the GR712RC (LEON3 dual core) or the GR740 (LEON4 quad core).

Achievements and status

The project delivered several improvements to the RTEMS SMP implementation:

• System initialization via constructors
• Scalable timer/timer support
• Giant lock removal (replaced by scalable fine grained locking)
• OMIP implementation (transitive priority inheritance to clustered scheduling)

These features were developed and tested on the two target platforms, GR712RC and GR740, but also support the PowerPC (QorIQ: P1020, P2020, T2080, T4240), ARM v7 (Altera Cyclone V, Xilinx Zync, Raspberry PI2) and ARM v8 platforms.

Benefits

The project has provided a high performance and scalable SMP implementation for use in near real-time embedded systems (note that modern multicore architectures with shared cache are limited in their time predictability, so hard real-time constraints are difficult to achieve). From the programming perspective, there are now many options to exploit the power of these novel multicore architectures: both C11 and C++11 threads, POSIX pthreads, OpenMP and MTAPI are fully supported. The SMP implementation is part of the generic RTEMS open source main-line (https://www.rtems.org/), starting from version 5.1. The final report and final presentations of this activity are available through http://microelectronics.esa.int/gr740/index.html

Next steps

A follow-up activity is planned to qualify the RTEMS SMP implementation for software criticality level C, aimed at use for applications in the scope of payloads. This activity will provide the qualification evidence needed to qualify an application using RTEMS on bespoke hardware based on either GR712RC or GR740, in compliance to the ECSS-E-ST-40C and ECSS-Q-ST-80C standards.