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| ||Predefined VDHL models for board-level simulation|
Predefined packages used for models intended for board-level simulation.
The following packages are predefined and should be located their corresponding VHDL libraries.
In this package the enumerated type SimConditionType is defined, to be used to select Worst, Typical or Best Case values for timing parameters in VHDL models for Board-level simulation. (vhd)
This package defines three array types, indexed by the SimConditionType, needed for timing generics when using Vital Delay Types. The types are intended to be used in VHDL models for Board-level simulation. (vhd)
The two packages above should not be modified or moved to a different library.
IEEE.Vital_Timing Package Header
IEEE.Vital_Timing Package Body
This package defines standard types, attributes, constants, functions and procedures for use in developing ASIC models. Specifically a set of subprograms for timing checking are defined.
IEEE.Vital_Primitives Package Header
IEEE.Vital_Primitives Package Body
This package defines standard types, constants, functions and procedures for use in developing ASIC models. Specifically a set of logic primitives are defined.
Last update: 26 June 2007
Related codeESA.Simulation (vhd)ESA.Timing (vhd)