ESA - Microelectronics - The use of reprogrammable FPGAs in space

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FLIPPER Product Sheet Suitability of reprogrammable FPGAs in space applications Functional Triple Modular Redundancy (FTMR) About us

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Technologies for Space

Microelectronics Technologies for Space

The use of reprogrammable FPGAs in space

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Microelectronics Development Methodology VHDL The use of FPGA in space VDHL models for board-level simulation

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System-On-Chip (SOC) Development IP-Cores for SOC Developments in Space Applications SOC Development Activities The AMBA Bus System Documents Related to SOC and IP-Core-Based Design

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Virtual Platform Technology

The use of reprogrammable FPGAs in space

Reprogrammable (SRAM based) FPGA (RFPGA), featuring high flexibility, combined with high performance and complexity become increasingly important also for space applications. With satellite lifetimes increased far beyond 10 years, much longer than the validity of telecom standards, reprogrammability in flight becomes a stringent requirement. If software solutions are not possible, RFPGA may soon be the only solution. In contrary to ASIC or one-time (antifuse) programmable FPGA, the configuration of RFPGA is stored in an SRAM, which is sensitive to SEU's. The radiation behaviour of RFPGA and methods for SEU mitigation is investigated in several studies.

FLIPPER Product Sheet

The FLIPPER test system has been developed by IASF Milano under an ESA contract. FLIPPER allows the injection of SEU-like faults into the user flip-flops, configuration memory and reconfiguration control registers of a Xilinx FPGA. This allows for the impact of configuration SEUs on unprotected designs to be tested, as well as the efficiency of fault mitigation methods to be evaluated. The Executive Summary of this activity is available for download, along with a Product Sheet.

Author: Monica Alderighi, IASF – INAF, Milano (pdf available)

Suitability of reprogrammable FPGAs in space applications

"Field Programmable Gate Array (FPGA) devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation. But with the advent of reprogrammable devices featuring a million systemgates or more, it is not longer feasible to disregard these technologies." This document concentrates on SRAM based FPGA devices from Xilinx. Through a comprehensive bibliography, it illustrates SEU failure mechanisms and susceptibility, SEU mitigation approaches and summarises (radiation) test results.

Author: Sandi Habinc (pdf available)

Functional Triple Modular Redundancy (FTMR)

"VHDL Design Methodology for Redundancy in Combinatorial and Sequential Logic" Further expands the 'logic replication and voting in combinatorial and sequential logic', mentioned in the previous document. In particular implementing redundancy in combinatorial logic is a challenge, since commercial synthesis tools aim to remove any logic redundancy. A VHDL coding method is developed, which reliably allows to infer configurable levels of redundancy in registers and combinatorial logic. Code examples are given as well as synthesis and layout results.

Author: Sandi Habinc (pdf available)

Last update: 27 March 2009

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