ESA
Home
Space Engineering
Electrical
About us
ESA Microelectronics Section
Workshops and Conferences
Contact us
Technologies for Space
Microelectronics Technologies for Space
The use of reprogrammable FPGAs in space
ESA IP Cores
About ESA IP Cores
IP Cores Library
CAN - HDL
CUC-CTM - HDL
EDAC - HDL
EVI32 - HDL
IP1553 - HDL
LEON2-FT - HDL
OBDH - HDL
PDEC - HDL
PTCD - HDL
PTME - HDL
RT53EUR - HDL
SpaceWire-AMBA - HDL
SpaceWire-b - HDL
SpaceWire-RMAP - HDL
Authentication Unit - HDL
VCA, VCM, TCE - HDL
SystemC IP-Cores
Usage Statistics
Licensing
Events
IP Cores Workshop 2005
Contact us
Development Methodology
Microelectronics Development Methodology
VHDL
The use of FPGA in space
VDHL models for board-level simulation
System-On-Chip (SOC)
System-On-Chip (SOC) Development
IP-Cores for SOC Developments in Space Applications
SOC Development Activities
The AMBA Bus System
Documents Related to SOC and IP-Core-Based Design
On Board Components
Ongoing ASIC developments
Completed ASIC developments (recent)
Completed ASIC developments (older)
System Level Modeling
Electronic System-Level Design Methodology
System-Level Modeling in SystemC
SystemC IP-Cores Library
LEON2/3 Integer Unit - SystemC
SpaceWire-b CODEC - SystemC
Virtual Platform Technology
Search
Article Images
WIC
Area/Speed Results
Back to article
Download:
HI-RES JPEG
(Size:
72 kb
)
Top-level diagram of the Flexwave-II
Last update: 26 June 2007
Related documents
Flexwave Documentation Package (zip)
WIC Synthesis Results (txt)
Copyright 2000 - 2012 © European Space Agency. All rights reserved.
HI-RES JPEG (Size: 
