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Contents A structured VHDL design methodVHDL Modelling GuidelinesThe VHDL Standard ReportThe Usage of VHDL in the European Space AgencyAccelerated Verification of Digital Devices Using VHDLVHDL Models for Board-level SimulationVHDL Models for Board-level Simulation Source Code ExamplesESA.Simulation About us
Technologies for Space ESA IP Cores
ASIC Developments History System Level Modeling
The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs, the communication of hardware design data, and the maintenance, modification, and procurement of hardware.
VHDL is the preferred language in developments initiated or led by the European Space Agency.
Author of both documents: Jiri Gaisler, Copyright Gaisler Research (pdf available)
A structured VHDL design method
In order to overcome the limitations of the classical 'dataflow' design style (large number of concurrent VHDL statements and processes, leading to bad readability and increased simulation time), a 'two-process' coding method is proposed: one process contains all combinational logic, whereas the other process infers all (and only) the registers. The paper further introduces the use of record types to increase readability and the safe use of variables to reduce simulation time. The method has been applied on several designs made by or for ESA. A presentation/lecture is also available.
VHDL Modelling Guidelines
The purpose of these guidelines is to ensure a good coding standard for VHDL, w.r.t. to readability, portability and a high level of verification. There are separate sections dealing with specific requirements for VHDL models for component simulation, board-level simulation, system-level simulation and testbenches. Author: Peter Sinander (pdf available)
The VHDL Standard Report
An overview of the current (May 1994) status of the VHDL standard and associated activities within the IEEE, EIA, and ESPRIT projects. An extensive summary of VHDL repositories is included, together with a list of European VHDL tools. (pdf available)
The Usage of VHDL in the European Space Agency
Outlines how VHDL is used in European Space Agency activities, in particular focusing on the need for modelling guidelines and an approach to use VHDL for board-level simulation.
Author: Peter Sinander (pdf available)
Accelerated Verification of Digital Devices Using VHDL
This paper presents two aspects for improving the verification of microprocessors; program-less verification, and methods for handling large differences in abstraction level between a reference model and the actual design. Program-less verification is a type of pseudo random verification where the notion of a software program executing on the microprocessor has been abandoned.
Author: Sandi Habinc and Peter Sinander (ESA/ESTEC TOS-ESM) (pdf available)
VHDL Models for Board-level Simulation
This document provides recommendations for development and usage of VHDL models intended for Board-level simulation. The purpose of these recommendations is to define modelling criteria that will produce models that are highly accurate in both functionality and timing, and that will provide sufficient simulation performance to facilitate long simulation runs.
Author: Sandi Habinc (pdf available)
VHDL Models for Board-level Simulation Source Code Examples
Source code examples to the document above.
In this package the enumerated type SimConditionType, to be used to select Worst, Typical or Best Case values for timing parameters in VHDL models for board-level simulation. (vhd file available)
Last update: 13 July 2007
Related documentsA Structured VHDL Design Method (pdf)A Structured VHDL Design Method, Presentation lecture (pdf)VHDL Modelling Guidelines (pdf)The VHDL Standard Report (pdf)The Usage of VHDL in the European Space Agency (pdf)Accelerated Verification of Digital Devices Using VHDL (pdf)VHDL Models for Board-level Simulation (pdf)
Related codeESA.Simulation, SimConditionType (vhd code)