Microelectronics Technologies for Space
One of the main tasks of the Microelectronics Section is to ensure the availability of suitable FPGA and ASIC technologies for users in the space community. The specific constraints of space projects (e.g. radiation environment, high reliability, low order quantities, long product lifetimes and long development cycles) have to be considered.
Developing dedicated space (and/or military) processes is one solution to this problem, which used to be done in former times (e.g. the DMILL = Durci Mixte Isolant Logico Lineaire, which became obsolete in 2003). In the FPGA domain, the Actel RT series is an example of dedicated high-rel/space development, which is still being further developed by the manufacturer. However, the increasing cost of for deep sub-micron process development, combined with low chip quantities makes it more and more difficult to justify dedicated developments.
Radiation effects (total dose, latchup, single event upsets) are one of the main concerns for space microelectronics. As radiation tolerance can often be achieved purely 'by design', i.e. by the schematics and layout of the chip, not only by process hardening, the use of commercial wafer fabs appears to be an attractive alternative for space microelectronics.
However, there are a number of challenges in using commercial technologies:
The following section presents our activities in the domain of technology:
Space Multi-Project-Wafer (MPW)
The 0.18 RHA technology is a spin-off of Atmel's commercial 0.18 um technology, developed under a contract led by CNES and the ESA Quality Department. The Microelectronics Section has initiated a MPW programme, to allow sharing the high cost for mask and wafer manufacturing and therefore make this technology available also for smaller projects and companies.
The DARE library development
DARE (= Design Against Radiation Effects) is a digital standard cell library developed on the UMC 0.18 um technology. By the means of specific layout and flip-flop redundancy, total dose, latchup and SEU immunity is achieved. Design kits have been developed, and the technology has been successfully evaluated with dedicated test chips and an application design (DROM). This technology can be procured through the Europractice IC service. (pdf available)
Last update: 15 October 2012