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| | | | | | | Internal Research
This section presents a summary of the internal research done by various Young Graduate Trainees, Spanish Trainees, Stagiaires and Research Fellows in the Microelectronics Section. Further down below we list some conference/workshop papers presented by members of the the section.
OCP: Open Core Protocol
An ESA internal case study, converting the CAN IP core to OCP
Date: June 2006
Author: Marta Posada (ppt available)
Magillem SOC Development
System On Chip Development Based on Magillem 2.3SE.
Date: December 2005
Author: Mattias Carlqvist (pdf)
SystemC Methodology
Research on New Design Methodology using SystemC.
Date: August 2005
Author: Nicolas Lainé (pdf)
80S32 Board
Specification of a Validation Board for the 80S32 8-bit Microcontroller.
Date: May 2003
Author: Sami Heinisuo (pdf)
GalileoSim
The objective of the activity was to develop a signal generator for GALILEO and GPS signals. At first, a software signal generator was implemented in Matlab. The software signal generator has to serve to rapidly prototype different transmitter configurations, algorithms and techniques, assess the performance of GALILEO signals, and create initial designs for further hardware implementations. Then, the signal generator was ported to VHDL code. A hardware implementation, e.g. on FPGA, will introduce higher efficiency due to its higher processing speed, allowing real-time generation of the signal.
Date: January 2003
Author: Juan Jose Borras Aguilar, YGT at ESTEC
(pdf)
PCI-AMBA
PCI Core - AMBA Bus interface.
Date: Nov. 2000
Author: Elsa Lama Vaquero (pdf)
PCI-Annex
Additional documentation on the PCI core developed by R. Locatelli.
Date: March 2000
Author: Elsa Lama Vaquero (pdf)
PCI-Core
Development of a Master/Target PCI VHDL Core.
Date: Sep. 1999
Author: Riccardo Locatelli (pdf)
CSD-FilterBank
ASIC Implementation of a Filter Bank Analyzer Based on CSD Code.
Date: Sept. 1999
Author: Christian Rosadini (pdf)
ACS & FFT
YGT Report in 2 parts: Digital Autocorrelation Spectrometers for Space-Borne Applications and Design of a Parallel FFT Processor Using Fixed Point Arithmetic and CSD Multiplication.
Date: August 1995
Author: Roland Weigand, YGT at ESTEC (pdf)
Last update: 16 March 2011 | |
| | Related documents InFault (pdf)OCP: Open Core Protocol (ppt)SEE Analysis and Mitigation (pdf)Magillem SOC Development (pdf)SystemC Methodology (pdf)80S32 Board (pdf)GalileoSim (pdf)TTC01 (pdf)PDFE (pdf)PCI-AMBA (pdf)PCI-Annex (pdf)PCI-Core (pdf)CSD-FilterBank (pdf)ACS & FFT (pdf)Related links ReSP info & downloads
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