OPS-SAT is devoted to demonstrating drastically improved mission control capabilities that will arise when satellites can fly more powerful on-board computers. It consists of a satellite that is only 30cm high but that contains an experimental computer that is ten times more powerful than any current ESA spacecraft.
It is very difficult to perform live testing in the domain of mission control systems. No-one wants to take any risk with an existing, valuable satellite, so it is very difficult to test new procedures, techniques or systems in orbit. The OPS-SAT solution is to design a low-cost satellite that is rock-solid safe and robust even if there are any malfunctions due to testing.
The robustness of the basic satellite itself will give ESA flight control teams the confidence they need to upload and try out new, innovative control software submitted by experimenters; the satellite can always be recovered if something goes wrong.
Achieving this level of performance and safety at a low cost is a challenge. To do this, OPS-SAT combines off-the-shelf subsystems as typically used with cubesats, the latest terrestrial microelectronics for the on-board computer and the experience ESA has gained in operating satellites for the last 40 years in keeping missions safe.
The result is an open, flying 'laboratory' that will be available for in-orbit demonstration of revolutionary new control systems and software that would be too risky to trial on a 'real' satellite. By the end of 2013, over 100 companies and institutions from 17 European countries have registered experimental proposals to fly on OPS-SAT.
OPS-SAT will be an in-orbit test-bed for:
- On-board software applications
- Advanced communication protocols
- Compression techniques
- Demonstration of advanced software-defined radio concepts
- Optical communication from ground to space
- Experiments using cameras, attitude control, scheduling and autonomy
Experiments with ground-based applications can also be hosted.
The in-orbit laboratory will offer a range of resources, including processors, field-programmable gate arrays (FPGAs), cameras, and an attitude determination and control system, all of which experimenters will be able to exploit for demonstrating new mission and operations concepts.
To satisfy the OPS-SAT objectives, a platform containing state-of-the-art semiconductor technologies, in particular very powerful computing platforms and FPGAs, is required in orbit.
The OPS-SAT architecture consists of two major parts. The first part is the OPS-SAT bus responsible for providing the necessary infrastructure to allow the operation of the second part, which is the payload. However, in this case, once the payload is running it can take over control of the entire satellite while the bus monitors and is ready to take control back at any moment.
The payload itself consists of a processing platform comprising a powerful System-on-Module and mass memory, a fine-pointing Attitude Determination and Control System (ADCS) including a star tracker, a CCSDS-compatible S-band transceiver, a high-speed X-band transmitter, a GPS receiver, a high-definition camera, an optical receiver and a software-defined radio receiver.
OPS-SAT provides a reliable architecture for in-orbit experiments. The execution of the experiments is constantly monitored and any failure of an experiment will not compromise the mission. Each hardware payload is also attached safely to the underlying bus system guaranteeing that any loss or malfunction of one subsystem will not affect the rest of the system. Redundancies are foreseen for the processing platform since it is the most critical part of the mission.
The OPS-SAT Bus will provide the necessary infrastructure to operate the payload. It comprises the following subsystems:
On-Board Computer (OBC)
The OBC is responsible for monitoring and control of the whole spacecraft.
FDIR Computer (OBC)
The FDIR computer is responsible fault detection and recovery of the payload and spacecraft at system level.
Coarse Attitude Determination and Control System (ADCS)
The objective of this subsystem is to recover and de-tumble the satellite in safe-mode and provide coarse-pointing.
Electrical Power System (EPS), including solar panels and batteries
The EPS allows OPS-SAT to generate sufficient power for all operational modes.
Basic low-data rate telemetry and telecommanding can be performed over a UHF link.
All OPS-SAT bus telemetry will be accessible via an API for the experiments as well as telecommands not restricted due to safety reasons. All housekeeping/payload telemetry and command history will be made available on the ground for post-processing by the experimenters.
The OPS-SAT is comprised of the following payload:
The heart of the OPS-SAT satellite payload is the processing platform which is responsible for providing a reconfigurable environment to fulfil the experiment objectives.
The processing platform running Linux as operating system consists of a flexible and reconfigurable framework featuring sophisticated processing capabilities, interfaces, memory integrity and reconfigurable logic:
- A powerful System-On-Module (e.g. Critical Link MityARM 5CSX)
- Altera Cyclone V SoC
- ARM dual-core Cortex-A9 MPCore
- 800MHz max clock speed
- Dual NEON SIMD Coprocessors
- 64 KB on-chip RAM
- ECC support
- Hard Processor System
- 1 MMC/SD/SDIO
- Up to 2 master/2 slave SPI
- Up to 4 I2C controllers
- Altera 5 CSTD5 FPGA fabric
- Up to 110,000 logic elements
- Up to 112 DSP blocks
- Enhanced Internal Memory protection (ECC, scrubbing)
- ARM dual-core Cortex-A9 MPCore
- 1GB-DDR3 CPU RAM (ECC-RAM)
- 32 MB QSPI NOR flash
- Altera Cyclone V SoC
- Delkin Industrial Grade SD Card
- 8 GB
- SLC memory
- ECC protection
OPS-SAT experimenters will provide bootable images for this processing platform. These images will undergo certain pre-checks before loading to the spacecraft. For example they will have to provide an external watchdog for the OBC monitoring. Power consumption and temperature of the processing core will also be monitored by the OBC to provide additional safety mechanisms.
An integrated fine ADCS will be providing the experimenters with access to sensors and actuators as well as integrated attitude control functionality.
The following performance is expected:
- Attitude Knowledge: 30 arcsec (using star tracker)
- Pointing Accuracy: << 1°
An I2C interface will provide the access to the following sensors:
- 3 axis gyro
- 3 axis accelerometer
- 3 axis magnetometer
In addition access to the following actuators is provided via I2C:
- 3 reaction wheels
- 3 magnetorquers
- Star Tracker
A GPS module extending the functionality of the ADCS is provided; the experimenters can have access to positioning data and time information.
Output parameters: Position, Velocity, Time, PPS Signal
- Position: typ. 10 m, max. 20 m
- Velocity: typ. 0.15 m/s, max. 0.25 m/s"
- Sync to UTC: ± 500 ns (TBC)
For high data rate communications a CCSDS-compatible S-band communication link acting as the main link for data communications and TM/TC with ESA ground stations is provided. It will provide uplink speeds of up to 256 kbit/s and downlink speeds of up to 1 Mbit/s. The S-band link will be used to upload experimenter’s’ software and download results of on-board experiments.
X-band transmitter with high-data-rate communications of up to 50 Mbit/s.
Every part of the OSI layer from the synchronization and coding layer up to the application layer can be changed. The only part fixed is the physical layer comprising modulation / demodulation and the RF interface.
A high-resolution camera is foreseen in the design, which can provide less than 80 m/pixel resolution (exact performance of this camera is still under discussion).
An optical receiver will be provided that can receive commands from a laser ranging station on Earth. An uplink rate of 2 kbps is expected.
Software defined radio
A software-defined radio front end will be provided, connected to one of the pair of diploes in the UHF antenna. The results of this experiment will be made available on the processing core for further processing by experimenters for, e.g., providing a flying spectrum analyser.
3 Bus systems are foreseen on the payload side:
- I2C: For low speed TM/TC used for status and control. Up to 400 kbit/s are possible on this bus in the high speed mode.
- SPI: For high speed data transfers (TM/TC). This will typically be used for the communication with the CCSDS Engine. Data rates can be arbitrary high depending on the SPI clock (but there are practical limitations of course).
- LVDS: Another high speed data transfer interface is the LVDS provided by the SoM. It allows the connection of very high speed sensors and peripherals (e.g. camera, S-Band transceiver).
Phase B2CDE kicked off on 4 February with the prime, TU Graz of Austria, and the subcontractors. Launch is expected Q3/Q4 2017.
The diagram shows the OPS-SAT interface, test and execution environment for experiments.
The interface between the experimenters, mission planning and operations is a server repository, where the experiments and their respective configurations are uploaded by the experimenters, and after execution on the validation benches the corresponding results, logs and data are made available.
Last update: 2 March 2015