PTCD - HDL
The Packet Telecommand Decoder (PTCD) IP core is a synthesizable VHDL model of the MA28140 chip from GEC-Plessey Semiconductors.
The PTCD IP core implements a complete CCSDS packet telecommand decoder,connected to the AMBA AHB and APB on-chip buses. The internal architecture of the PTCD IP is illustrated in the following diagram.
The underlying TM/TC functionality is described in detail in the data sheet of the MA28140 from GEC-Plessey Semiconductors with minor modifications.
Area on Xilinx Virtex-E
3500 LUT, 1000 DFF, 37 ext. I/O
Marc Souyri, Astrium SAS, 2002
Jean-Luc Boisdron, Astrium SAS, 2002
Nicolas Perrot, Astrium SAS, 2002
version 0.0, 12-March-2002
For a history of bug reports and fixes, modifications, upgrades, etc, please refer to the PTCD IP Core Release Notes.
Special licensing conditions
ESA can grant licenses for the use of the IP core only for activities performed in the frame of an ESA Programme.
Last update: 9 September 2011