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PDEC - HDL
 
The PDEC (Packet Telecommand Decoder) is a synthesizable VHDL core comprising:

- a complete CCSDS packet telecommand decoder (PDEC3),
- a Command Pulse Distribution Module (CPDM), and
- a Command Pulse Distribution Selector (CSEL),

all of them being integrated in an AMBA AHB wrapper.
 
Overview
 
The purpose of the PDEC synthesizable VHDL model is to provide the user with a single module implementing CCSDS/ESA compatible telecommand decoder and command pulse distribution unit with an AMBA Advanced High-performance Bus (AHB) interface.

The PDEC IP core is part of the Single Chip Telemetry and Telecommand (SCTMTC) ASIC that is currently being developed and validated by Saab Ericsson Space under an ESA contract.  
 

Architecture Diagram of the PDEC IP core
Architecture Diagram of the PDEC IP core
 
The functionality of PDEC3, CPDM and CSEL is described in the User's Manual of the SCTMTC ASIC (Issue 11, March 2006).

VHDL testbenches for this IP are available.
 
 
Area/Speed Results
 
Synthesis results for the PDEC (without I/O insertion)

Xilinx Virtex-E 200, -6 : 5877 LUTs, 3241 FFs, 31 MHz
Actel RT54SX72, -1 : 10657 COMB, 3714 SEQ, 17 MHz

Target frequency was 20 MHz
 
 
Developer
 
Sandi Habinc, Gaisler Research, 2003
 
 
Current Release
 
version 0.1, Nov-2003
 
 
Licensing limitations
 
ESA can grant licenses for the use of the IP core only for activities performed in the frame of an ESA Programme.
 
 
Last update: 9 September 2011

 


Related documents
PDEC Data Sheet (pdf)SCTMTC ASIC User Manual (pdf)SCTMTC Datasheet
Related links
CCSDSAMBA Home Page
 
 
 
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