PDEC - HDL
The PDEC (Packet Telecommand Decoder) is a synthesizable VHDL core comprising:
- a complete CCSDS packet telecommand decoder (PDEC3),
The purpose of the PDEC synthesizable VHDL model is to provide the user with a single module implementing CCSDS/ESA compatible telecommand decoder and command pulse distribution unit with an AMBA Advanced High-performance Bus (AHB) interface.
The PDEC IP core is part of the Single Chip Telemetry and Telecommand (SCTMTC) ASIC that is currently being developed and validated by Saab Ericsson Space under an ESA contract.
VHDL testbenches for this IP are available.
Synthesis results for the PDEC (without I/O insertion)
Xilinx Virtex-E 200, -6 : 5877 LUTs, 3241 FFs, 31 MHz
Target frequency was 20 MHz
Sandi Habinc, Gaisler Research, 2003
version 0.1, Nov-2003
ESA can grant licenses for the use of the IP core only for activities performed in the frame of an ESA Programme.
Last update: 9 September 2011