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Contents DevelopersCurrent ReleaseSpecial licensing restrictions About us Technologies for Space ESA IP Cores Development Methodology System-On-Chip (SOC) On Board Components System Level Modeling
| | | | | | | EDAC - HDL
The EDAC (Error Detection And Correction) IP Core is a set of encoders/decoders supporting data widths from 4 to 64 bits, providing Single Error Correction and Double Error Detection, and in some cases Double Error Correction and Single Bank-error Detection.
EDAC Encoders/Decoders are frequently used for protecting data in aerospace applications.
Area/Speed Results
Actel 54SXA - 54SX08A
(Please note that the EDAC implementation is purely combinational).
EDAC_RTL Total Cells 367 of 768 (48%)
EDAC_RTL combinatorial Cells 367 of 512 (72%)
Developers
- Sandi Habinc (ESA), 2000
- M. S. Hodgart, Surrey Satellite Technology Ltd (SSTL), 1999
- H. A. B. Tiggeler, Surrey Satellite Technology Ltd (SSTL), 1999
Current Release
version 0.6, August 2005
An encrypted Modelsim (5.6e) model is available for evaluation purposes.
For a history of bug reports and fixes, modifications, upgrades, etc, please refer to the EDAC IP Core Release Notes.
Special licensing restrictions
None.
Last update: 9 September 2011 | |
| | Related documents EDAC Core Overview (pdf)EDAC Release Notes (txt)Related links EDAC Simulation Model (for ModelSim 5.6e)
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