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Contents Area/Speed ResultsDeveloperCurrent ReleaseSpecial licensing restrictions About us Technologies for Space ESA IP Cores Development Methodology System-On-Chip (SOC) ASIC Developments History System Level Modeling
| | | | | | | SpaceWire-AMBA - HDL
A synthesizable VHDL core implementing the SpaceWire Encoder/Decoder with FIFOs (for Xilinx Virtex-E technology) and AMBA AHB master/slave interfaces.
Overview
The SpaceWire-AMBA IP core was initially developed by Astrium SAS, France, in the frame of the ESA 13345/#3 contract " Building block for System on a Chip" (a contract related to the design of a System On a Chip for Space applications).
The overall architecture of the SpaceWire-AMBA IP Core is illustrated in the following diagram (click on thumbnail to enlarge):
Area/Speed Results
SpaceWire-AMBA Architecture Diagram
Typical synthesis area targeting Virtex-E:
spacewire_amba : 1143 DFF, 1906 LUT, 4 BLKRAM
spacewire_noamba: 483 DFF, 475 LUT, 2 BLKRAM
Typical frequency (without external constraints) on Virtex-E:
75 MHz on the host interface clock
120 MHz on the RX/TX clocks.
Developer
Tam Le Ngoc, Astrium SAS, 2001
Current Release
version 1.2, May 2003
Beta version (v00) can be downloaded as encrypted Modelsim (5.6e) objects for evaluation purposes.
For a history of bug reports and fixes, modifications, upgrades, etc, please refer to the SpaceWire-AMBA IP Core Release Notes.
Special licensing restrictions
The SpaceWire-AMBA IP core incorporates the IEEE 1355 High Performance Serial Bus Std (Data/Strobe interface) patented by STMicroelectronics, so an appropriate STMicroelectronics patent notice must be included in the licenses and the final products.
Last update: 16 March 2011 | |
| | Related documents Specification and Architecture (pdf)User Manual (pdf)SpW-AMBA Release Notes (txt)Implementation of the SpW Clock Recovery Logic in Actel RTAX-S Devices (pdf)Related links ESA SpaceWire - HomeSpW-AMBA Simulation Model (for ModelSim 5.6e)
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