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| | | | | | | Schedulability analysis
The main work performed in the domain of schedulability analysis is related to the Ravenscar profile.
Ravenscar
The Ravenscar profile is a subset of the Ada tasking features suited for use in high-integrity, efficient real-time systems. Benefits of this tasking model are reduced size, faster execution and deterministic behaviour of the runtime system. Work is ongoing to standardise the profile under the auspices of ISO. Further information can be found in ‘The Ravenscar Profile’ (an outline of the profile), ‘The Ravenscar Tasking Profile for High Integrity Real-Time Programs’ (an article on the profile and its implementation) and the ISO working draft (a pre-final version of the ISO technical report ‘Programming Languages - Guide for the Use of the Ada Programming Language in High Integrity Systems’ where the Ravenscar profile is being incorporated).
Products
ESA/ESTEC have supported the definition of the profile and specifically invested in the development of two Ada Ravenscar products for ERC32:
- Open Ravenscar Real-Time Kernel (ORK) - see Overview of ERC32 Tools - ORK section
- Aonix Raven (Raven) - see Overview of ERC32 Tools - Raven section
The Worst Case Execution Time (WCET) Analysis of an ORK application report presents an analysis of an application using the compilation system and kernel GNAT/ORK. The aim is to demonstrate the feasibility of analysing GNAT/ORK based programs with respect to their timing properties using the static analysis Bound-T (now with Tidorum). Furthermore the report describes how this analysis is best done and the limitations of such techniques.
The ESA Ravenscar Benchmark (ERB) is a compiler test suite to evaluate efficiency (size and performance) of available compiler systems and kernels for ERC32 and Leon, and of different language constructs, kernel functions, and library implementations.
Schedulability Analysis with cache
The presence of a cache in the processor generates some non-determinism about the execution time. Disabling the cache causes the processor to under-perform drastically and is not acceptable. The WCET estimation, the scheduling policy and the cache policy need to be analysed. This matter is the subject of a current study with Tidorum, Rapita and Alcatel. The German tool vendor AbsInt also has some experience in this domain.
Last update: 21 March 2007 | |
| | More information Ravenscar outline (pdf)Ravenscar paper (pdf)Ravenscar draft ISO standard (pdf)Ravenscar in Ada95 (pdf)Caches in timing analysis (pdf)ESA Ravenscar Benchmark (ERB) on AdaCore web siteRelated articles Overview of ERC32 toolsRelated links Open RavenscarAonix RavenTIDORUMRAPITA Systems LtdAbsInt
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