Microelectronics Development Methodology
ASICs (Application Specific Integrated Circuits) and FPGA (Field Programmable Gate Arrays) are now commonly used on-board spacecraft. On top of the normal constraints and tools for ASIC/FPGA developments, reliability and radiation tolerance are of particular concern in space applications, and therefore, specific design methods and tools and standards are required. Part of our work aims also at investigating methodologies from commercial chip development and COTS tools used therein.
ECSS-Q-HB-60-02A (DIR 1) "Techniques for radiation effects mitigation in ASICs and FPGAs handbook"
This new ECSS Handbook is now in PUBLIC REVIEW until the 11th of January of 2016 and downloadable from
If you have any suggestions to improve its contents please forward them to ECSS Secretariat using the feedback form provided on-line by ECSS.
Complementing this Handbook, the following two documents are available for download at this site:
ECSS-Q-HB-60-02A Annex (informative) Vendor- or institute-ready ASIC and FPGA technology solutions that include mitigation against radiation effects or that can help to introduce mitigation and/or to validate it
The ECSS-Q-HB-60-02 handbook provides a compilation of different techniques that can be used to mitigate the adverse effects of radiation in integrated circuits (ICs), with special attention to Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) to be used in space.
The target users of this handbook are developers and users of ICs which are meant to be used in a radiation environment. Following a bottom-up order, the techniques are presented according to the different stages of an IC development flow where they can be applied. Therefore, users of this handbook can be IC engineers involved in the selection, use or development of IC manufacturing processes, IC layouts and ASIC standard cell libraries, analogue and digital circuit designs, FPGAs, embedded memories, embedded software and the immediate electronic system (printed circuit board) containing the IC that can experience the radiation effects .
In addition, this handbook contains a short overview of the space radiation environment and its effects in semiconductor devices, a section on how to validate the good implementation and effectiveness of the mitigation techniques, and a special section providing some general guidelines to help with the selection of the most adequate mitigation techniques.
The information given in this handbook is provided as guidelines and for reference, and not as requirements.
ESA IP Core Technical Requirements
The objective of this document is to describe the technical requirements and the minimum set of deliverables expected, in order to allow a design to be reused as an “Intellectual Property Core”, or IP core. The main subject of this document is the “soft IP cores”, i.e. IP cores that are delivered to the Agency as synthesizable RTL HDL code. (pdf available)
The ECSS ASIC/FPGA Development Standard
In a joint initiative between ESA, Tesat and the European Cooperation for Space Standardisation (ECSS), and with participation from reviewers in European industry, a new ASIC/FPGA Development Standard has been elaborated, which shall become the reference standard for space developments. The latest version of the standard (ECSS-Q-ST-60-02C) was issued by ECSS in July 2008, replacing the previous version from July 2007 (ECSS-Q-60-02A). The standard is made available at this site. (pdf available)
The standard is also available for public download (in both PDF and DOC formats) from the ECSS website, in the "Space Product Assurance Standards" section (requires registration).
FT-UNSHADES is a test system dedicated to the study of Fault Tolerant Circuits and the measurement of the robustness of an ASIC netlist against soft errors. It is based on a proprietary method for inserting controlled modifications into the current state of the emulator device (Xilinx Virtex-II, XC2V4000, XC2V6000, XC2V8000) during execution time. Using this board and software, fault tolerance detailed analysis can be produced before IC fabrication. The project was designed and engineered by a team of researchers from the Electronics Engineering Department of the University of Seville under an ESA contract.
The SEUs Simulation Tool (SST)
The SEUs Simulation Tool (SST) is a set of Perl and TCL scripts which allow the injection of SEU-like faults into HDL and netlist simulations.
The Design Under Test (DUT) is analyzed, and a list of nodes is provided to the user. After user selection of a fault scenario, appropriate TCL "force" commands are generated for the simulator (ModelSim), which will then upset selected nodes of the design at the selected time during simulation. (pdf available)
- Author : Daniel Gonzalez Gutierrez
The tool is provided for free download under GPL licence. However, if you download and use this tool, please inform us by sending a mail to IpCoreRequest[at]esa.int and provide feedback/bugfixes to this same address. (zip file available)
Feel free to also visit the SST page at University Antonio de Nebrija, containing release 2.0 (November 2006). (see "Related links").
ASIC Design and Manufacturing Requirements
This document is used for ESA technology development contracts to minimise development risks and avoid "unpleasant surprises" late in the development. This document forms one part of the inputs to the ECSS-Q-60-02A standard for ASIC development, officially published by the ECSS on July 17th, 2007.
The final draft of the ECSS-Q-60-02 standard is available for download from this page. The official release of this standard (ECSS-Q-60-02A) is available for public download from the ECSS website, under the "Space Product Assurance Standards" section (requires registration). (pdf available)
ASIC Design and Assurance Requirements
This document represents the precursor of a specification of the same scope and objectives intended for issue within the ESA Procedures, Specifications and Standards, branch of Product Assurance and Safety (PSS-01 series). It establishes the basic requirements for the development of ASIC components, ASIC specific quality assurance requirements, prototype manufacture, testing and validation which are to be applied by ESA contractors and subcontractors. This document is referenced and complemented by the ASIC Design and Manufacturing Requirements.
- Author: Ralf de Marino (pdf available)
Last update: 20 November 2015