Enabling & Support

IP-Cores for SOC Developments in Space Applications

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics
  • IP-Cores available from ESA

Synthesisable IP-Cores, mostly in VHDL language, developed by ESA or under ESA contract, which can be licensed under certain conditions.

 

  • LEON2(-FT) Sparc V8 Development

The LEON2 core is a SPARC V8 compatible processor developed for future space missions, based on the AMBA AHB and APB on-chip buses. The LEON2-FT is a Single-Event-Upset (SEU) fault-tolerant version of the LEON2 core, implemented as a highly configurable, synthesizable VHDL model, involving complete TMR protection for all flip-flops and EDAC protection for all memories. The LEON2-FT core is the base of the Atmel AT697 microprocessor, implemented in a radiation hardened 0.18um ASIC process. A test-chip (LEONUMC) has also been implemented by the Microelectronics Section in commercial 0.18um technology from UMC.

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