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| About us Technologies for Space ESA IP Cores Development Methodology System-On-Chip (SOC) On Board Components System Level Modeling 
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| | Related documents User Manual (pdf)VHDL Verification (pdf)SpW-b Release Notes (txt)Implementation of the SpW Clock Recovery Logic in Actel RTAX-S Devices (pdf)Related links ESA SpaceWire - HomeSpaceWire Yahoo! GroupSpaceWire-b CODEC - SystemC | ||||||||||||||||||||||||
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