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Space Engineering

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Technologies for Space

Microelectronics Technologies for Space The use of reprogrammable FPGAs in space

ESA IP Cores

About ESA IP Cores

IP Cores Library

CAN - HDL CUC-CTM - HDL EDAC - HDL IP1553 - HDL LEON2-FT - HDL PDEC - HDL PTCD - HDL PTME - HDL RT53EUR - HDL SpaceWire-AMBA - HDL SpaceWire-b - HDL SpaceWire-RMAP - HDL Authentication Unit - HDL SCOC3 SpaceWire-RMAP - HDL CANopen Controller IP Core (CCIPC)

SystemC IP-Cores

Discontinued IP-Cores

VCA, VCM, TCE - HDL OBDH - HDL EVI32 - HDL WIC

Usage Statistics Licensing

Events

IP Cores Workshop 2005

Development Methodology

Microelectronics Development Methodology VHDL VDHL models for board-level simulation

System-On-Chip (SOC)

System-On-Chip (SOC) Development IP-Cores for SOC Developments in Space Applications SOC Development Activities The AMBA Bus System Documents Related to SOC and IP-Core-Based Design

ASIC Developments History

Ongoing ASIC developments Completed ASIC developments (recent)Completed ASIC developments (older)

System Level Modeling

Electronic System-Level Design Methodology System-Level Modeling in SystemC SystemC IP-Cores Library

LEON2/3 Integer Unit - SystemC SpaceWire-b CODEC - SystemC SoCROCKET Virtual Platform - SystemC

Virtual Platform Technology

Article Images

About ESA IP Cores

Last update: 25 January 2011

Related articles

Microelectronics Development Methodology IP-Cores for SOC Developments in Space Applications IP Cores Workshop 2005

Related links

Design & Reuse (D&R)ECSI Home Gaisler Research GRLIB OCP-IP OPENCORES.ORG SPIRIT Consortium VSI Alliance ESA IP Cores User's Forum

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