SystemC IP-Cores

In the past, the hardware design world standardized on two languages: VHDL and Verilog. Lately, there has been a growing interest in complementary languages that could be employed for descriptions at a much higher level of abstraction. The driving forces behind such efforts are the simultaneous increase in design complexity, with multi-million gate designs, and the increase in pressure to get designs out faster with first-time design success. Among those high-level languages, SystemC, System-Verilog, and SpecC represent the most widespread. These languages fuse a well-known syntax with powerful constructs, enabling the modeling and simulation of complex systems; in particular SystemC has grown more and more popular.

A Virtual Platform is a software based system that can fully mirror the functionality of a target System-on-Chip or board. These virtual platforms combine high-speed processor simulators and high-level, fully functional models of the hardware building blocks, to provide an abstract, executable representation of the hardware to software developers and to system architects.

ESA IP cores can generally be licensed to be usedin the frame of ESA contracts, orfor privately-funded activities.Depending on the particular IP core needed, restrictions on its usage might be present, so please refer to the web pages dedicated to each individual ESA IP core for more details.In any case, the procedure for requesting and licensing ESA IP cores is the same, and the following conditions apply:Licences can only be granted to companies or institutes that provide ESA with a duly completed IP Request Form.the scope of use of the ESA IP cores is limited to peaceful purposesno warranty or technical support is provided by ESA.