The use of reprogrammable FPGAs in space

The FLIPPER test system has been developed by IASF Milano under an ESA contract. FLIPPER allows the injection of SEU-like faults into the user flip-flops, configuration memory and reconfiguration control registers of a Xilinx FPGA. This allows for the impact of configuration SEUs on unprotected designs to be tested, as well as the efficiency of fault mitigation methods to be evaluated. The Executive Summary of this activity is available for download, along with a Product Sheet.

• Author: Monica Alderighi, IASF – INAF, Milano (pdf available)

"Field Programmable Gate Array (FPGA) devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation. But with the advent of reprogrammable devices featuring a million systemgates or more, it is not longer feasible to disregard these technologies." This document concentrates on SRAM based FPGA devices from Xilinx. Through a comprehensive bibliography, it illustrates SEU failure mechanisms and susceptibility, SEU mitigation approaches and summarises (radiation) test results.

• Author: Sandi Habinc (pdf available)

"VHDL Design Methodology for Redundancy in Combinatorial and Sequential Logic" Further expands the 'logic replication and voting in combinatorial and sequential logic', mentioned in the previous document. In particular implementing redundancy in combinatorial logic is a challenge, since commercial synthesis tools aim to remove any logic redundancy. A VHDL coding method is developed, which reliably allows to infer configurable levels of redundancy in registers and combinatorial logic. Code examples are given as well as synthesis and layout results.

• Author: Sandi Habinc (pdf available)

"The complexity of the designs that are made in FPGAs has increased at the same rate as for ASICs. In essence, the FPGA design task has become much more complex. It has never before been so easy to make so many mistakes so fast as now." Starting from a summary of things which went wrong in real life ("lessons learned"), this document is an extension to the two previous documents, suggesting a development/design methodology for FPGA and valuable recipees for single event mitigation in FPGA designs.

• Author: Sandi Habinc (pdf available)

This paper gives an overview of the audits that ESA made on several FPGA designs included in the Rosetta spacecraft. and to assess any potential problems and their solutions at spacecraft and/or operational level. MAPLD, September 2002.

• Authors A. Fernandez-Leon, A. Pouponnot, S. Habinc (pdf available)