ESAHomeSpace EngineeringElectrical
About us
Technologies for Space
ESA IP Cores
Development Methodology
System-On-Chip (SOC)
ASIC Developments History
System Level Modeling
printer friendly page
VDHL models for board-level simulation
This page contains the VHDL source code examples described in the document VHDL Models for Board-level Simulation. The document provides recommendations for development and usage of VHDL models intended for Board-level simulation. All models for Board-level simulation delivered to ESA should be developed in accordance with VHDL Modelling Guidelines.

Board-level simulation can be defined as simulating the functionality of one or several printed circuit boards built with standard components, possibly incorporating Application Specific Integrated Circuits, ASIC, and Application Specific Standard Products, ASSP. Board-level simulation is also known under the names rapid or virtual prototyping and sometimes system simulation. The purpose of Board-level simulation is to verify the behaviour of the board design.

The complete example directory containing the VHDL code example has been tared and compressed for convenient retrieval.  
Last update: 26 June 2007


Related articles
Predefined VDHL models for board-level simulationModel for board-level simulationVerification of models for board-level simulationBoard designsVerification of board designs
Related documents
VHDL Modelling Guidelines (pdf)VHDL Models for Board-level Simulation (pdf)
   Copyright 2000 - 2014 © European Space Agency. All rights reserved.