Enabling & Support

Model for board-level simulation

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

A model for board-level simulation is characterised by its accurate modelling of the component behaviour, simulation performance, and ease of use for board designers.

Hierarchy for models for board-level simulation is introduced to obtain good source code readability and to separate different modelling aspects. The outlined hierarchy scheme below is based on two of these aspects, namely timing and functionality. Since these usually stem from two different lines of documentation and representation, the Data Sheet and the Component model, the model should be partitioned taking this into account. A partitioning also enables separate verification of the two domains of the model.

The example below shows how a model for board-level simulation of a Bit Modulator has been implemented. Only parts of the model have been completed, but should be sufficient to present the modelling ideas. The following design units are located in the library BitMode_Lib (vhd):


The timing parameters should be defined as deferred constants in a separate package, allowing the values to be changed by only re-analysing the package body. (vhd)

BitMod (BoardLevel)

The timing checking in the model should be contained in the BoardLevel architecture, including setup and hold time checking, clock-to-output and propagation delay scheduling. (vhd)


Configuration specifications in the architecture should be avoided, allowing the usage of the more flexible configuration declarations outside the models. (vhd)


This package defines conversion functions used for the BitMod design which are not contained in the IEEE Std_Logic_1164 package. (vhd)

BitMod_Core (Behavioural)

The functionality of the device should be modelled in the functional core, and be independent of timing. There should not be more entities comprising the functional core than there are blocks in the architectural block diagram. (vhd)

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