Electronic System-Level Design Methodology

In the past, the hardware design world standardized on two languages: VHDL and Verilog. Lately, there has been a growing interest in complementary languages that could be employed for descriptions at a much higher level of abstraction. The driving forces behind such efforts are the simultaneous increase in design complexity, with multi-million gate designs, and the increase in pressure to get designs out faster with first-time design success. Among those high-level languages, SystemC, System-Verilog, and SpecC represent the most widespread. These languages fuse a well-known syntax with powerful constructs, enabling the modeling and simulation of complex systems; in particular SystemC has grown more and more popular.

Various activities have been or are being undertaken to create high level models of the VHDL IP-Cores most used in the Systems-on-Chip (SoCs) employed at the European Space Agency. Examples of such IP-Core include the LEON2 and LEON3 processor cores, restricting the modeling to the integer unit; the other elements which are indeed part of the LEON2/3 SoCs are being developed as separate SystemC IP-Cores. Some of them are the L1 cache, Sparc V8 Reference MMU, Interconnection compliant with the AMBA© AHB™ and APB™ protocols, Memory Controller, etc. For more details see the individual pages about the IP-Core models and the SoCROCKET Virtual Platform. Additional IP-Cores which are currently part of the NGMP Architecture are also being considered. The following Figure shows the current development status: green blocks indicates IP-Cores under development, blue completed and available, and black not yet under development.

A Virtual Platform is a software based system that can fully mirror the functionality of a target System-on-Chip or board. These virtual platforms combine high-speed processor simulators and high-level, fully functional models of the hardware building blocks, to provide an abstract, executable representation of the hardware to software developers and to system architects.

The continuous increase of transistor density on a single die is leading towards the production of more and more complex systems on a single chip, with an increasing number of components starting to be integrated into a single System-on-Chip (SoC): a single device containing multiple functions, e.g. processor, memory, communication primitives, etc. To support the design of those complex systems, new families of tools are needed. They are generally grouped in the branch known as Electronic System Level (ESL) and they provide support for tasks like design space exploration, system level verification, and performance analysis. The ESA Electronic System-Level design presentation day focuses on the activities that are being undertaken at the European Space Agency in order to start introducing some of those tools in the design and development cycles of digital electronics for space. In particular, the presentations will focus on techniques to efficiently create and use models at a higher than RTL abstraction, and especially on how to employ them to enable concurrent design of the hardware and software design portions. It will be demonstrated how, often, this brings added value with respect to classical RTL design approach.