Advanced ASIC and FPGA technologies allow to integrate complex systems on a single chip, embedding standard processor devices, dedicated processing blocks, interfaces to various peripherals, on-chip bus structures in a SOC, or even analog blocks in a mixed-signal device. Moving away from the use of traditional components towards SOC technology will help to satisfy the ever-increasing demands for high processing performance, while reducing mass and power consumption.
With increasing complexity, the design methodology has changed from being gate-level oriented to the integration of complex building blocks (IP-cores). Tasks, which traditionally are considered as 'system-design', such as interface specification, bus throughput assessment etc. are now part of the chip design. The designers have to rely on pre-existing building blocks, ideally with already verified functionality, documentation and production test vectors being available. But different IP-blocks from various origins imply different coding styles, documentation and verification levels. Their interoperability and compliance to the overall SOC specification ultimately has to be verified on chip level.
Besides the technical issues, core-based design is also a challenge on the legal side, when it comes to the integration of IP blocks from various origins, bound to different licensing conditions, prices and non-disclosure agreements.
The European Space Agency promotes the use of SOC in space by the means of SOC development activities, IP-core development/distribution and documentation relating to on-chip bus systems and design methodology. These activities are presented in the following sections.