|005 - Abstract:|
|An international organisation has developed has developed a synthesisable VHDL core implementing the SpaceWire Encoder/Decoder according to standard ECSS-E-ST-50-12C, with FIFOs and AMBA AHB master/slave interfaces. License agreement collaboration is sought.|
Description of the offer:
SpaceWire is a reliable, high speed serial link compliant with the ECSS-E-50-12 specification. The VHDL core contains AMBA AHB interfaces for the integration into a System-on-Chip. The SpaceWire receives packets of data from the host through the AHB interface. Two modes are possible for this data transfer. The first one is the AHB master mode, which performs the transfer with a DMA mechanism. With the descriptor of a linked list of packets given by the host, SpaceWire retrieves 32-bit data of each packet of the linked list. The second one is the AHB slave mode. In this mode, the host transfers the length of the packet and the 32-bit data of the packet to the SpaceWire.
Domain of Application:
All domains requiring high reliable high throughput off-chip interconnection networks, for example;