Enabling & Support

IPMON

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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

The IP Monitoring (IPMON) module is used to spy an AHB Bus, recording trace and statistics data. This
IP was designed in the context of the SCOC3 project but can be used as a generic AHB spy module.

Overview

The following blocks compose the IPMON IP-Core (as shown in the Figure below):

  • The AHB slave interface is used to read statistics and trace data into Memory block,
  • The Trace Controller is used to trace AHB signals from AHB bus,
  • The Statistics Controller is used to calculate statistics data from AHB bus,
  • The Memory block is used to store trace and statistics data,
  • The Trig Controller is used to command Trace Controller and Statistics Controller with trigger conditions,
  • The APB Interface is used to configure trigger registers and read Status registers.

The Trace Block traces SEQ and NON-SEQ accesses on the AHB bus. These data are stored in a Trace
buffer. The size of the Trace buffer is programmable (using a constant) from 64 to 1024 words of 128 bits.

IPMON Block diagram
IPMON Block diagram

Collected Statistics

The following statistics are collected by the IP-Core:

  • cumulative number of responses with HRESP equal to ‘OK’, ‘ERROR’, ‘RETRY’ or ‘SPLIT’.
  • cumulative number of Wait States (HREADY low).
  • cumulative Grant Delay (delay between HBUSREQ = ‘1’ and HGRANT = ‘1’), i.e. master latency
  • number of accesses with HTRANS = NON-SEQ or HTRANS = SEQ (IDLE and BUSY transfers are not taken into account).
  • number of locked accesses (accesses with HMASTLOCK = ‘1’).
  • cumulative length of a locked transfers for master/slave pairs.
  • cumulative length between an HRESP=SPLIT response and the address phase of the next transfer time for master/slave pairs.

IPMON also allows defining the trigger conditions for the trace controller and for the statistics controller.

IPMON Integration in an AMBA-based system
IPMON Integration in an AMBA-based system

Area and Speed Results

The core is generic RTL code which can be synthesized for a range of ASIC and FPGA technologies including Actel and Xilinx FPGAs.
Examples of resource usage on some Xilinx technologies is given below; note that no significant effort was spent in trying to optimize those results.

Virtex 5Q – XQ5VFX130T:

Number of Used Slice Registers: 1139 (1%)
Number of Used Slice LUTs: 2898 (3%)
Number of occuppied slices: 1169 (5%)
Number of BRAMs: 8 (2%)

Max clk frequency: 88MHz

Developers

Astrium - O. Corvoisier, Marc Soury - 2008

Licensing Conditions

No special licensing conditions apply. For more information refer to the ESA IP-Cores licensing page.

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