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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

MIL-STD-1553B Remote Terminal IP Core.


The RT53EUR IP core is a classic 1553B Remote Terminal. When used in nominal and redundant mode, it is connected to the 1553B bus with the following elements:

• Two single 1553B Transceivers, or a dual 1553B Transceiver
• Two 1553B Transformers
• A stable oscillator that delivers the IP clock frequency

The connection of the RT53EUR IP core to a 1553B bus is as shown in the figure below.

RT53EUR bus connections
RT53EUR bus connections

The RT53EUR IP core can be functionally divided in 2 parts: the 1553B interface and the Application Interface. The RT53EUR contains the following functions:

• A nominal and a redundant Manchester decoder
• A nominal and a redundant Manchester encoder
• A redundancy management function
• A protocol management function
• An application management function

The block diagram of the RT53EUR IP core is depicted in the figure below.

RT53EUR Block Diagram
RT53EUR Block Diagram

For more detailed information on the RT53EUR IP core please refer to the design documentation. The User Manual and Data Sheet are available for direct download from the menu on the right.

Area/Speed Results

The RT53EUR is delivered as a generic technology netlist format, and can be targeted to any ASIC or FPGA technology, including Actel and Xilinx FPGAs. As an indication, the area/speed results when targeting an Actel RTAX2000 FPGA are as follows:

Actel RTAX2000
- Combinational Cells : 2782 of 21496 (13%)
- Sequential Cells : 960 of 10752 ( 9%)
- Total Cells : 3742 of 32248 (12%)
- Clock frequency : 55.5 MHz (functional frequency from 10 MHz to 24 MHz in steps of 2 MHz)


Marc Souyri, Astrium SAS, 2009
Yannick Coquereau, Astrium SAS, 2009
Arnaud Wagner, Astrium SAS, 2009

Current Release

Version 1.3, 20-June-2013

Special licensing restrictions

ESA can grant licenses for the use of the RT53EUR IP core only for activities funded by the Agency (ESA projects).
Please also note that the RT53EUR IP core can only be delivered in VHDL generic technology netlist format, without the full RTL VHDL source code being disclosed.

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