ESA title
Enabling & Support


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ESA / Enabling & Support / Space Engineering & Technology / Microelectronics

A synthesizable VHDL core implementing the SpaceWire Encoder/Decoder with FIFOs (for Xilinx Virtex-E technology) and AMBA AHB master/slave interfaces.


The SpaceWire-AMBA IP core was initially developed by Astrium SAS, France, in the frame of the ESA 13345/#3 contract " Building block for System on a Chip" (a contract related to the design of a System On a Chip for Space applications).


The overall architecture of the SpaceWire-AMBA IP Core is illustrated in the following diagram (click on thumbnail to enlarge):

Area/Speed Results

SpaceWire-AMBA Architecture Diagram
SpaceWire-AMBA Architecture Diagram

Typical synthesis area targeting Virtex-E:
spacewire_amba : 1143 DFF, 1906 LUT, 4 BLKRAM
spacewire_noamba: 483 DFF, 475 LUT, 2 BLKRAM

Typical frequency (without external constraints) on Virtex-E:
75 MHz on the host interface clock
120 MHz on the RX/TX clocks.


Tam Le Ngoc, Astrium SAS, 2001

Current Release

version 1.2, May 2003

Beta version (v00) can be downloaded as encrypted Modelsim (5.6e) objects for evaluation purposes.

For a history of bug reports and fixes, modifications, upgrades, etc, please refer to the SpaceWire-AMBA IP Core Release Notes.

Special licensing restrictions

The SpaceWire-AMBA IP core incorporates the IEEE 1355 High Performance Serial Bus Std (Data/Strobe interface) patented by STMicroelectronics, so an appropriate STMicroelectronics patent notice must be included in the licenses and the final products.

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