High Density European Rad-Hard SRAM-Based FPGA- First Validated Prototypes – BRAVE
| Programme: | TRP Workplan | Achieved TRL: | 5 |
| Reference: | T701-301ED | Closure: | 2017 |
| Contractor(s): | NanoXplore (FR), STMicroelectronics(FR) | ||
Field Programmable Gate Arrays (FPGAs) are versatile components that implement a wide range of digital functions and are present in almost all digital electronic units across all ESA missions. The need for competitive European FPGAs that enable flexibility, high performance and miniaturization has been harmonized with agencies and the space industry. This strategic development has been originally defined and co-funded between ESA and CNES.
Objective(s)
The goal of this activity is to define, design, verify, manufacture and validate the first medium-capacity, high-performance, radiation-hardened re-programmable European FPGA (NG-MEDIUM) and its development kit.
It is the first FPGA of the Big Re-programmable Array for Versatile Environments (BRAVE) FPGA family.
Achievements and status
The BRAVE NG-MEDIUM has been designed, verified, manufactured using 65nm CMOS technology from STMicroelectronics.
The NG-MEDIUM prototypes have been functionally validated.
Two radiation test campaigns have confirmed the expected radiation performance that has been achieved using Radiation Hardened By Design (RHBD) techniques.
The Development Kit has been designed, manufactured and integrated; and is available for customers.
The FPGA tools have been developed self-funded by NanoXplore (budget not included in the slide).
Benefits
This first BRAVE FPGA provides a competitive solution to develop electronic units for space. It is already being analyzed by a large number of companies. The BRAVE FPGAs flexibility through re-programmability, miniaturization and faster performance are key enabler of the Space 4.0.
Next steps
The qualification of BRAVE NG-MEDIUM is included in the EC H2020 project VEGAS with the goal to have Space qualified part available by Q3CY18. The FPGA tools independent quality evaluation has just started in a TRP activity. The next steps which consists to develop more dense FPGA devices with features fitting with user requirements are already ongoing.
