ESA title
Enabling & Support

IP Cores Library

1377 views 3 likes
ESA / Enabling & Support / Space Engineering & Technology / Microelectronics


ESA HDL IP Cores Portfolio Overview

Below is a list of our current IP Cores. Click on each link to get more information.



AHBR The AHBR IP-Core implements an AMBA AHB to AMBA AHB bus bridge, where the two busses are clock synchronous clocks with defined frequency ratio function.
AUIP The Authentication Unit (AU) Intellectual Property (IP) core is a synthesizable VHDL model that contains functionality for Telecommand (TC) authentication using the Advanced Encryption Standard (AES). The functionality also includes Key management and Logical Authentication Channel) LAC management.
CAN The design of the Controller Area Network (CAN) VHDL IP core started as a prototype activity with the intention to understand the internal of a CAN (Controller Area Network) controller and not to develop the full controller.
CCIPC The CANopen Controller IP Core (CCIPC)implements a large subset of the CANopen services as defined in the CAN in Automation (CiA) Standard “CANopen Application Layer and Communication Profile”.
CUC-CTM CUC-CTM stands for "CCSDS Unsegmented Code (CUC) & CCSDS Time Manager (CTM)".
EDAC The EDAC (Error Detection And Correction) IP Core is a set of encoders/decoders supporting data widths from 4 to 64 bits, providing Single Error Correction and Double Error Detection, and in some cases Double Error Correction and Single Bank-error Detection.
FTADDR FTADDR is a memory controller for DDR2 and DDR3 type of SDRAM memory devices. On the memory side, it presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the systemon-chip, it presents the memory through an AMBA AHB slave interface.
IP1533 The IP1553 IP core implements a Mil-Std-1553 interface. It is compatible with the MIL-STD-1553B (notice 2) protocol and manages three different working modes: Bus Controller, Remote Terminal, and Bus Monitor. It can be used to develop equipment for Space Applications.
IPMON The IP Monitoring (IPMON) module is used to spy an AHB Bus, recording trace and statistics data. This IP was designed in the context of the SCOC3 project but can be used as a generic AHB spy module.
LEON2-FT The LEON2-FT processor is the SEU (Single Event Upset) tolerant version of the LEON2 processor. Flip-flops are protected by Triple Modular Redundancy and all internal and external memories are protected by EDAC or parity bits.
PDEC The PDEC (Packet Telecommand Decoder) is a synthesizable VHDL core comprising: a complete CCSDS packet telecommand decoder (PDEC3), a Command Pulse Distribution Module (CPDM), and a Command Pulse Distribution Selector (CSEL), all of them being integrated in an AMBA AHB wrapper.
PTCD The Packet Telecommand Decoder (PTCD) IP core is a synthesizable VHDL model of the MA28140 chip from GEC-Plessey Semiconductors.
PTME The Packet Telemetry Encoder (PTME) is a synthesizable VHDL IP core, comprising a complete CCSDS packet telemetry encoder. It includes the following blocks: Virtual Channel Assemblers, associated to various input interfaces (Packet-APB, Packet-Wire, Packet-Asynchronous-RS232 and Packet-Parallel), Virtual Channel Multiplexer, and Telemetry encoder chain (including Reed-Solomon encoder, and Convolutional encoder). The core is highly configurable at compile (synthesis) time and at runtime, and it is extensively documented.
RT53EUR The RT53EUR IP core is a classic 1553B Remote Terminal. When used in nominal and redundant mode, it is connected to the 1553B bus with the following elements: Two single 1553B Transceivers, or a dual 1553B Transceiver, Two 1553B Transformers, A stable oscillator that delivers the IP clock frequency.
SHyLoC SHyLoC comprises the VHDL description of two synthesizable IP cores that implement lossless data compression algorithms as defined by the CCSDS 123.0-B-1 and CCSDS 121.0-B-2 standards.
SpW-AMBA A synthesizable VHDL core implementing the SpaceWire Encoder/Decoder with FIFOs (for Xilinx Virtex-E technology) and AMBA AHB master/slave interfaces.
SpWb Synthesizable VHDL core implementing the SpaceWire Codec (including testbenches).
SpW-RMAP-Astrium The SpaceWire-RMAP IP core implements the Remote Memory Access Protocol (RMAP) extensions to SpaceWire. RMAP provides a standard mechanism for reading from, and writing to memory in a remote SpaceWire node.
SpW-RMAP-Dundee The SpaceWire-RMAP IP core implements the Remote Memory Access Protocol (RMAP) extensions to SpaceWire. RMAP provides a standard mechanism for reading from, and writing to memory in a remote SpaceWire node.
SpWTDP The aim of the Time Distribution Protocol (TDP) is to synchronize time across a SpaceWire network.
SpaceFibre Port IP Core A synthesizable VHDL implementation of a single-lane SpaceFibre port.This IP was initially developed by Cobham Gaisler AB, Sweden, in the frame of ESA contract 4000116134/15/NL/LF.
SCCC IP Core IP Core for medium data rate PDT, compliant with CCSDS 131.2-B-1 standard.

Discontinued IP Cores

VCA, VCM, TCE - HDL The separate IP's for Virtual Channel Assembler (VCA), Virtual Channel Multiplexer (VCM) and the Telemetry Channel Encoders (Reed-Solomon, Convolutional and Turbo Encoder) have been merged into - and are superseded by - the PTME IP Core.
OBDH The DOCC (DHS On-board Communication Controller) core features Control and Remote Terminal (CT/RT) functionality for OBDH (On-board Data Handling), DHS (Data Handling System, PSS-04-255) and RTU-kernel.
EVI32 ERC32 VMEbus Interface (EVI32) - specification, synthesizable VHDL model and ASSP component
WIC The WIC (Wavelet Image Compression) is a synthesizable VHDL model based on the Ocapi Flexwave IP developed by IMEC.
The WIC IP Core supports both lossy and lossless compression modes.